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公开(公告)号：US5382915A
公开(公告)日：1995-01-17
申请号：US85900
申请日：1993-07-06
申请人： David L. Muri , Robert E. Stengel
发明人： David L. Muri , Robert E. Stengel
CPC分类号： H03F3/2171
摘要： An audio amplifier (100) switches between a pulsewidth-modulated (PWM) mode to an analog mode when required in order to reduce unwanted EMI when the signals being reproduced fall within a predetermined threshold range such as when reproducing low amplitude signals. Amplifier (100) includes both a pulsewidth-modulator (114) and a low-level analog amplifier (126) coupled to a speaker bridge circuit. When controller (106) determines that the input signal (102) is at a predetermined level, controller (106) selectively applies to the load (164) an analog signal instead of the PWM signal, this provides for improved dynamic range and reduced amplifier produced EMI.
摘要翻译： 当需要时，音频放大器（100）在脉冲宽度调制（PWM）模式到模拟模式之间切换，以便当再现的信号落在诸如当再现低振幅信号的预定阈值范围内时，减少不必要的EMI。 放大器（100）包括耦合到扬声器电桥电路的脉宽调制器（114）和低电平模拟放大器（126）。 当控制器（106）确定输入信号（102）处于预定电平时，控制器（106）选择性地向负载（164）施加模拟信号而不是PWM信号，这提供了改进的动态范围和减小的放大器产生 EMI。
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62.发明授权Method and apparatus for providing power conservation in a communication system 失效在通信系统中提供功率节省的方法和装置
公开(公告)号：US5265270A
公开(公告)日：1993-11-23
申请号：US709044
申请日：1991-06-03
CPC分类号： H04B1/1027 , H04B1/1615 , H04L1/20 , H04W52/0238
摘要： A communication device 200 capable of operating in a communication system 100 having a control system which generates information signals with redundant information is disclosed. The communication device comprises: a receiver 214 for receiving the information signals; a circuit which can determine the signal quality of the received information signals 234; and a controller 226 which decodes the received information signals, and further compares the signal quality of the information signals with a predetermined value, and decides if the received signal quality is at least equal to the predetermined value in order to only decode a portion of the information signal. Upon the communication device decoding a portion of the information signal, the communication device 200 is placed in a battery saving mode in order to conserve battery life.
摘要翻译： 公开了能够在具有生成具有冗余信息的信息信号的控制系统的通信系统100中进行操作的通信装置200。 通信设备包括：接收器214，用于接收信息信号; 可以确定接收到的信息信号234的信号质量的电路; 以及对所接收的信息信号进行解码的控制器226，并且将信息信号的信号质量与预定值进行比较，并且判定所接收的信号质量是否至少等于预定值，以便仅解码部分 信息信号。 在通信装置对信息信号的一部分进行解码时，为了节省电池寿命，通信装置200被置于电池节电模式。
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公开(公告)号：US20140062605A1
公开(公告)日：2014-03-06
申请号：US13601488
申请日：2012-08-31
IPC分类号： H03L7/16
CPC分类号： H03L7/16 , H03L7/099 , H03L7/1974 , H03L7/23 , H03L7/24
摘要： A synthesizer architecture, responsive to a low noise reference signal from a discrete oscillator, provides a continuous periodic output with a period that is a fractional multiple of the low noise reference signal. One exemplary embodiment includes a phase detector providing a control signal to a selected one of a plurality of integrated voltage controlled oscillators (VCO), wherein the phase detector is a sub-harmonic continuous time sampling phase detector. Another exemplary embodiment includes a continuous fractional divider input to the phase detector in response to an output of the selected VCO. Yet another exemplary embodiment comprises an injection locked ring oscillator responsive to the low noise narrow band variable reference signal with a fractional output period.
摘要翻译： 响应于来自离散振荡器的低噪声参考信号的合成器架构提供了具有低噪声参考信号的分数倍的周期的连续周期性输出。 一个示例性实施例包括相位检测器，其向多个集成压控振荡器（VCO）中的所选择的一个提供控制信号，其中相位检测器是次谐波连续时间采样相位检测器。 另一示例性实施例包括响应于所选择的VCO的输出的相位检测器的连续分数分频器输入。 另一个示例性实施例包括响应于具有小数输出周期的低噪声窄带可变参考信号的注入锁定环形振荡器。
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公开(公告)号：US20110156781A1
公开(公告)日：2011-06-30
申请号：US12650649
申请日：2009-12-31
IPC分类号： H03L7/08
CPC分类号： H03L7/1974
摘要： A frequency generation unit is provided that permits a receiver to tune from channel to channel without cycle skipping and in which compensation for phase offset introduced during tuning is provided. The frequency generation unit includes a fractional-N synthesizer, a voltage controlled oscillator (VCO), and a direct digital synthesizer (DDS). The fractional-N synthesizer generates frequencies from the VCO as well as a temperature controlled crystal oscillator. Outputs from the fractional-N synthesizer are supplied both the VCO and the DDS to control the VCO and DDS. The combination of the voltage controlled oscillator and fractional-N synthesizer is perpetually locked. The fractional-N synthesizer is maintained in a locked condition. The VCO output is provided to the DDS. An output from the DDS or from the fractional-N synthesizer forms the output signal of the frequency generation unit.
摘要翻译： 提供了频率产生单元，其允许接收器在没有周期跳过的情况下从信道调谐到信道，并且在提供在调谐期间引入的相位偏移补偿。 频率产生单元包括分数N合成器，压控振荡器（VCO）和直接数字合成器（DDS）。 分数N合成器从VCO产生频率以及温度控制的晶体振荡器。 来自分数N合成器的输出都由VCO和DDS提供，以控制VCO和DDS。 压控振荡器和分数N合成器的组合永久锁定。 分数N合成器保持在锁定状态。 VCO输出提供给DDS。 来自DDS或分数N合成器的输出形成频率产生单元的输出信号。
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65.发明授权公开(公告)号：US07773713B2
公开(公告)日：2010-08-10
申请号：US11584410
申请日：2006-10-19
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H04L7/0012
摘要： A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.
摘要翻译： 公开了用于编程直接数字合成器的时钟数据恢复的系统和方法。 计数器用于计算接收到的数字信号的时钟频率的粗略测量，采用分接延迟线来计算接收的数字信号的时钟频率的精细测量。 粗略和精细的测量用于计算用于编程直接数字合成器的值以产生作为接收的数字信号的时钟频率的近似副本的时钟信号。
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公开(公告)号：US07620133B2
公开(公告)日：2009-11-17
申请号：US10983447
申请日：2004-11-08
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , H03K5/133 , H03K5/135 , H03K2005/00286 , H03L7/0812 , H04L7/0337
摘要： A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.
摘要翻译： DPC（300）包括：用于产生时钟信号的频率源（310）; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于生成包括顺序逻辑设备（500,510,520）和组合网络的输出信号的加窗选择电路。 一种在DPC中使用的方法包括：基于识别延迟线上的第一输出抽头的期望输出信号接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头以接收至少两个不同的相移时钟信号; 以及基于所述控制信号和所接收的基本上是所需输出信号的相移时钟信号来产生（420）输出信号。
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67.发明授权Direct digital synthesizer with variable reference for improved spurious performance 有权具有可变参考的直接数字合成器，可提高杂散性能公开(公告)号：US07570096B2
公开(公告)日：2009-08-04
申请号：US11861860
申请日：2007-09-26
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/131 , H03K2005/00065 , H03L7/1806
摘要： Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.
摘要翻译： 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。
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68.发明授权System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis 有权用于引入抖动以减少数字到时间转换器直接数字合成的系统和方法公开(公告)号：US07421464B2
公开(公告)日：2008-09-02
申请号：US10954571
申请日：2004-09-30
IPC分类号： G06F1/02
CPC分类号： G06F1/025 , G06F2211/902
摘要： A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).
摘要翻译： 一种直接数字合成器（DDS）（300），其使用用于减少数字 - 时间转换器（DTC）中的杂散发射的系统（317）。 DDS（300）包括一个或多个抖动源（307）和随机存取存储器（RAM）（305）。 RAM（305）通过使用与抖动源（307）组合的查找表的输出来利用查找表来存储延迟误差值，以补偿DTC（317）中的不相等的单位延迟值。
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公开(公告)号：US07409012B2
公开(公告)日：2008-08-05
申请号：US10172566
申请日：2002-06-14
IPC分类号： H04L27/20
CPC分类号： H04L27/2007
摘要： Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).
摘要翻译： 提供了相移键调制器（100,500,1000,1400,1700），其中使用多相信号源（108,1402,1406-1412,1702）来产生载波信号的多个相位。 选择器（110）用于选择载波信号的相位或相位序列，以表示从二进制数据源（102,1422）接收的每个位模式。 多相信号源优选地包括多相振荡器，其包括可变传播延迟反相器（202）的锁相环。 优选地，相位序列器（502）用于选择相位的单调序列以表示每个位模式。 优选地，两个相位选择器（110,1004）用于同时选择载波信号的两相，并且相位内插器（1106）用于从由两个相位选择器（110,1004）选择的两相中产生相位序列， 。
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70.发明授权Direct digital synthesizer with variable reference for improved spurious performance 有权具有可变参考的直接数字合成器，可提高杂散性能公开(公告)号：US07315215B2
公开(公告)日：2008-01-01
申请号：US11370689
申请日：2006-03-08
IPC分类号： H03L7/08
CPC分类号： H03H11/265 , H03K5/131 , H03K2005/00065 , H03L7/1806
摘要： Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.
摘要翻译： 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。
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