Write protection control for electronic assemblies
    61.
    发明授权
    Write protection control for electronic assemblies 失效
    写入电子组件的保护控制

    公开(公告)号:US06765826B2

    公开(公告)日:2004-07-20

    申请号:US10226684

    申请日:2002-08-23

    IPC分类号: G11C1604

    CPC分类号: G11C16/22 G06F12/1433

    摘要: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

    摘要翻译: 本发明涉及具有可写写保护特征的非易失性存储器件和用于从电子组件的电源端的电位产生写保护信号的开关配置的电子组件。

    Semiconductor module having a configurable data width of an output bus, and a housing configuration having a semiconductor module
    62.
    发明授权
    Semiconductor module having a configurable data width of an output bus, and a housing configuration having a semiconductor module 有权
    具有输出总线的可配置数据宽度的半导体模块和具有半导体模块的壳体配置

    公开(公告)号:US06765302B2

    公开(公告)日:2004-07-20

    申请号:US10266322

    申请日:2002-10-08

    IPC分类号: H01L2348

    摘要: A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.

    摘要翻译: 具有输出总线的可配置数据宽度的半导体模块具有数据连接焊盘以及具有连接到相关联的数据连接焊盘的相应输出的驱动器电路。 在操作期间不用于交换数据或命令的数据连接焊盘中的至少一个永久地连接到用于内部电源电压的连接。 因此,在使用数据线数量减少的模块配置中,由于提高了信号对地比,所以剩余的数据线可以以增加的频率工作。

    Receiver immune to slope-reversal noise

    公开(公告)号:US06492836B2

    公开(公告)日:2002-12-10

    申请号:US09726984

    申请日:2000-11-30

    申请人: Oliver Kiehl

    发明人: Oliver Kiehl

    IPC分类号: H03K19017

    摘要: A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring a rising edge or a falling edge in accordance with a control signal. The second stage also includes a feedback loop coupled to an output of the second stage. The feedback loop provides the control signal for switching the switching circuit to favor the rising edge or falling edge.

    Flexible ECC/parity bit architecture
    64.
    发明授权
    Flexible ECC/parity bit architecture 失效
    灵活的ECC /奇偶校验位架构

    公开(公告)号:US5966389A

    公开(公告)日:1999-10-12

    申请号:US603409

    申请日:1996-02-20

    申请人: Oliver Kiehl

    发明人: Oliver Kiehl

    CPC分类号: G06F11/1008

    摘要: A semiconductor memory device is disclosed which includes an input terminal for receiving, and an output terminal for producing a data word, each having a predetermined number of bits. An internal memory array stores a plurality of error correcting encoded codewords each encoding more than one data word. An error correcting encoder is coupled between the input terminal and the memory array for generating an error correcting encoded codeword, encoding the received data word, and storing the codeword in the internal memory array. An error correcting decoder is coupled between the internal memory array and the output terminal to retrieve an error correction encoded codeword from the internal memory array, correct any detected errors, and produce one of the more than one data words encoded in the retrieved codeword at the output terminal.

    摘要翻译: 公开了一种半导体存储器件,其包括用于接收的输入端子和用于产生每个具有预定位数的数据字的输出端子。 内部存储器阵列存储编码多于一个数据字的多个纠错编码码字。 纠错编码器耦合在输入端和存储器阵列之间,用于产生纠错编码码字,对接收到的数据字进行编码,并将码字存储在内部存储器阵列中。 纠错解码器耦合在内部存储器阵列和输出端子之间以从内部存储器阵列检索纠错编码的码字,校正任何检测到的错误,并产生编码在所检索的码字中的多于一个的数据字中的一个 输出端子。

    Fully differential digital-to-analog converter with a low number of
resistors
    65.
    发明授权
    Fully differential digital-to-analog converter with a low number of resistors 失效
    具有低数量电阻的全差分数模转换器

    公开(公告)号:US5838273A

    公开(公告)日:1998-11-17

    申请号:US907526

    申请日:1997-08-08

    摘要: A fully differential resistor-string digital-to-analog converter wherein a resistor network having half the number of resistors of an otherwise standard digital-to-analog convertor of this type is enabled with the assistance of a first decoder, a second decoder and a subtraction unit thus reducing the required chip area and the overall switching time.

    摘要翻译: 一种完全差分电阻串数模转换器,其中具有这种类型的其它标准数模转换器的电阻数量的一半的电阻器网络在第一解码器,第二解码器和 因此减少了所需的芯片面积和整个切换时间。

    Circuit configuration for adjusting the quadrature-axis current
component of a push-pull output stage
    66.
    发明授权
    Circuit configuration for adjusting the quadrature-axis current component of a push-pull output stage 失效
    用于调整推挽输出级的正交轴电流分量的电路配置

    公开(公告)号:US5485123A

    公开(公告)日:1996-01-16

    申请号:US301709

    申请日:1994-09-06

    申请人: Oliver Kiehl

    发明人: Oliver Kiehl

    IPC分类号: H03F1/32 H03F3/18 H03F3/30

    摘要: A circuit configuration for adjusting the quadrature-axis current component of a push-pull output stage has two transistors of opposed conduction type and is triggered by an input signal. A variable being proportional to the quadrature-axis current component of the push-pull output stage is derived from a comparison circuit. A final control element adjusts the quadrature-axis current components of the push-pull output stage and of the comparison circuit for matching the variable to a reference variable.

    摘要翻译: 用于调整推挽输出级的正交轴电流分量的电路配置具有两个相反导通型晶体管,并由输入信号触发。 与推挽输出级的正交轴电流分量成比例的变量从比较电路得出。 最终控制元件调整推挽输出级和比较电路的正交轴电流分量,以将变量与参考变量相匹配。

    ZAG fuse for reduced blow-current application
    67.
    发明授权
    ZAG fuse for reduced blow-current application 失效
    ZAG熔断器可减少吹风电流的使用

    公开(公告)号:US5420456A

    公开(公告)日:1995-05-30

    申请号:US193927

    申请日:1994-02-09

    IPC分类号: H01L21/82 H01L23/525 H02H7/20

    摘要: A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse. The predictability of the point of fuse blow out allows even greater circuit densities while minimizing the possibility of accidental damage to adjacent devices.

    摘要翻译: 具有降低的电流要求从而使驱动晶体管所需的电源电压和芯片面积最小化的保险丝具有几何形状,其特征在于在熔丝链的整个主轴上具有基本上均匀的宽度尺寸,但具有至少一个约 熔断体直角弯曲。 保险丝可以被吹开,其截面积相等的直线熔断器所需的输入电流密度约为10%。 这样做的原因是,由于目前的拥挤,电流密度在弯道的内角突出。 当保险丝的输入电流增加时,在内角处达到电流密度,导致保险丝材料熔化。 内角处形成凹痕。 通过开槽改变的保险丝几何在槽口处引起更严重的电流拥挤,这又导致熔化在保险丝的宽度上传播。 保险丝熔断点的可预测性允许更大的电路密度,同时最小化对相邻设备的意外损坏的可能性。