公开(公告)号：US6140449A

公开(公告)日：2000-10-31

申请号：US236589

申请日：1999-01-26

申请人： Shigeru Mori ,  Eiichi Tabei

发明人： Shigeru Mori ,  Eiichi Tabei

IPC分类号： C08K5/10 ,  C08G77/60 ,  C08K5/14 ,  C08K5/23 ,  C08L83/16 ,  C09D183/16 ,  C08G77/08

CPC分类号： C08G77/60 ,  C09D183/16

摘要： A crosslinkable silicon polymer composition is provided comprising (A) a silicon polymer containing Si--Si bonds and Si--H groups and having a Mn of 500-500,000, (B) a polyfunctional aromatic carboxylic acid allyl ester, and (C) an organic peroxide or azo compound. The composition cures into a crosslinked polysilane film which is solvent insoluble, tough, and abrasion resistant.

摘要翻译： 提供一种可交联的硅聚合物组合物，其包含（A）包含Si-Si键和Si-H基并具有500-500,000的Mn的硅聚合物，（B）多官能芳族羧酸烯丙基酯和（C）有机 过氧化物或偶氮化合物。 该组合物固化成溶剂不溶性，韧性和耐磨性的交联聚硅烷膜。

公开(公告)号：US5955192A

公开(公告)日：1999-09-21

申请号：US974501

申请日：1997-11-19

申请人： Motoo Fukushima ,  Yoshitaka Hamada ,  Shigeru Mori

发明人： Motoo Fukushima ,  Yoshitaka Hamada ,  Shigeru Mori

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H01L27/108 ,  H01L21/312 ,  H01L21/3205

CPC分类号： H01L23/49894 ,  H01L21/4846 ,  H05K3/185 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10T428/264 ,  Y10T428/2804 ,  Y10T428/2809

摘要： A conductive circuit board is prepared by forming a film of organopolysilane having a H-Si bond on a substrate, selectively exposing the organopolysilane film to light to form a photo-crosslinked layer in exposed areas, dissolving away unexposed areas, and contacting a silver salt with the photo-crosslinked layer and reducing the silver salt to form a silver conductive layer thereon. A conductive circuit board comprising a circuit-patterned film of photo-crosslinked polymer on a substrate and a silver conductive layer on the film has high and stable electric property.

摘要翻译： 通过在基板上形成具有H-Si键的有机聚硅烷膜，通过选择性地将有机聚硅烷膜暴露于光以在曝光区域形成光交联层，将未曝光区域溶解并将银盐接触而制备导电电路板 与光交联层并还原银盐以在其上形成银导电层。 包括基板上的光交联聚合物的电路图案化膜和膜上的银导电层的导电电路板具有高且稳定的电性能。

公开(公告)号：US5691661A

公开(公告)日：1997-11-25

申请号：US458775

申请日：1995-06-02

申请人： Tatsuya Fukuda ,  Shigeru Mori ,  Masanori Hayashikoshi ,  Seiji Sawada

发明人： Tatsuya Fukuda ,  Shigeru Mori ,  Masanori Hayashikoshi ,  Seiji Sawada

IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C11/406 ,  H03K3/03 ,  H03K3/354 ,  H03L1/02 ,  G11C11/34

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C5/147 ,  G11C7/22 ,  H03K3/0315

摘要： A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.

摘要翻译： 脉冲信号发生电路包括环形振荡器和内部电压产生电路。 内部电压产生电路根据操作温度产生内部电压。 内部电压在正常温度下为低电平，在高温下为高电平。 环形振荡器中的每个反相器由内部电压产生电路提供的内部电压驱动。 因此，脉冲信号的周期在正常温度下增加，并且在高温下降低。

公开(公告)号：USRE35613E

公开(公告)日：1997-09-23

申请号：US496569

申请日：1995-06-29

申请人： Kenichi Yasuda ,  Makoto Suwa ,  Shigeru Mori

发明人： Kenichi Yasuda ,  Makoto Suwa ,  Shigeru Mori

IPC分类号： H01L27/02 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

摘要翻译： 半导体存储器件包括第一导电类型的半导体衬底中的第一导电类型的阱，该第一导电类型的半导体衬底由第二导电类型阱围绕，存储单元和布置在第一导电类型阱上的外部输入电路之一，另一个位于第二导电类型 类型很好。 对第二导电类型阱施加预定的电源电压，并且将第一导电类型阱连接到地。 在该结构中，从外部输入电路注入的电荷载流子被吸收在第二导电型阱中。 结果，防止电荷载体到达存储单元并破坏其中存储的数据。 因此，可以使晶体管小型化并提高动态随机存取存储器件的集成密度，而不会使源极降低介电强度。

公开(公告)号：US5654924A

公开(公告)日：1997-08-05

申请号：US640639

申请日：1996-05-01

申请人： Tomio Suzuki ,  Motoko Hara ,  Shigeru Mori

发明人： Tomio Suzuki ,  Motoko Hara ,  Shigeru Mori

IPC分类号： G11C29/00 ,  G11C29/06 ,  G11C29/28 ,  G11C29/36 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C29/28 ,  G11C29/36

摘要： A semiconductor memory device is provided which can apply a voltage stress to every adjacent bit lines even when data is written using a data bit compression function in a burn-in test mode. More specifically, when data is written using the data bit compression function in the test mode, an input buffer circuit is brought to a state in which it receives a signal corresponding to a signal dq0 applied to a specific input/output terminal by a switch circuit controlled by a test mode specify signal TE in common. When an inversion designate signal INV is in an active state, a complementary signal corresponding to a signal obtained by inversion of signal dq0 by an inverting circuit is output to internal data buses IO0, ZIO0, and IO2, ZIO2. On the other hand, a complementary signal corresponding to signal dq0 is output to internal data buses IO1, ZIO1, and IO3, ZIO3.

摘要翻译： 提供了一种半导体存储器件，即使在老化测试模式下使用数据位压缩功能写数据时，也可以向每个相邻位线施加电压应力。 更具体地，当在测试模式中使用数据位压缩功能写入数据时，输入缓冲器电路进入其中通过开关电路接收与施加到特定输入/输出端子的信号dq0相对应的信号的状态 由测试模式控制，共同指定信号TE。 当反转指示信号INV处于活动状态时，与通过反相电路的信号dq0的反相获得的信号相对应的互补信号被输出到内部数据总线IO0，ZIO0和IO2，ZIO2。 另一方面，对应于信号dq0的互补信号被输出到内部数据总线IO1，ZIO1和IO3，ZIO3。

公开(公告)号：US5608682A

公开(公告)日：1997-03-04

申请号：US554503

申请日：1995-11-07

申请人： Shinichi Jinbo ,  Shigeru Mori

发明人： Shinichi Jinbo ,  Shigeru Mori

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： An address generating circuit and an address switching circuit of a DRAM output address signals A0 to A11 according to a refresh cycle time set by the user being less than a predetermined value, and output address signals A0 to A10 according to the refresh cycle time being the predetermined value or more. A row decoder selects one word line in response to the signals A0 to A11, and selects two word lines in response to the signals A0 to A10. Since refresh is carried out by selecting two word lines when the refresh cycle time is at the predetermined value or more, disappearance of data can be prevented.

摘要翻译： 根据由用户设定的刷新周期时间，DRAM输出地址信号A0〜A11的地址生成电路和地址切换电路，根据刷新周期时间，输出地址信号A0〜A10为 预定值以上。 行解码器响应于信号A0至A11选择一个字线，并响应于信号A0至A10选择两个字线。 由于当刷新周期时间在预定值以上时通过选择两条字线进行刷新，所以可以防止数据的消失。

公开(公告)号：US5600496A

公开(公告)日：1997-02-04

申请号：US397647

申请日：1995-03-02

申请人： Shigeru Mori

发明人： Shigeru Mori

IPC分类号： G03B13/36 ,  G02B7/02 ,  G02B7/08 ,  G02B7/28 ,  G02B15/14 ,  G02B15/16 ,  H04N5/232

CPC分类号： G02B15/14

摘要： A zoom lens device includes an imaging device for converting light from an object to an electrical signal, a zoom lens and a focusing lens disposed between the object and the imaging device, a zooming adjusting circuit for adjusting a movement of the zoom lens, focus adjusting circuits for adjusting movements of the focusing lens, correcting circuits for outputting an adjustment value in response to adjustment of the zoom lens, a temperature detecting circuit for detecting a temperature around the object, and a coefficient circuit for correcting a correction value of the correcting circuit based on an output signal of the temperature detecting circuit.

摘要翻译： 变焦透镜装置包括：用于将来自物体的光转换成电信号的成像装置，设置在物体和成像装置之间的变焦透镜和聚焦透镜;变焦调整电路，用于调节变焦透镜的移动;聚焦调节 用于调整聚焦透镜的运动的电路，响应于变焦透镜的调节而输出调节值的校正电路，用于检测物体周围温度的温度检测电路，以及用于校正校正电路的校正值的系数电路 基于温度检测电路的输出信号。

公开(公告)号：US5549851A

公开(公告)日：1996-08-27

申请号：US377342

申请日：1995-01-24

申请人： Motoo Fukushima ,  Mikio Aramata ,  Shigeru Mori

发明人： Motoo Fukushima ,  Mikio Aramata ,  Shigeru Mori

IPC分类号： H01B1/12 ,  H01B1/20 ,  H01B1/04 ,  H01B1/24

CPC分类号： H01B1/12

摘要： A silicon containing polymer such as a polysilane, poly(disilanylenephenylene), and poly(disilanyleneethynylene) is admixed with an amine compound and then doped with an oxidizing dopant, typically iodine and ferric chloride, to produce a highly conductive polymer composition having improved shapability. The composition is easily applicable, as by spin coating, to form a highly conductive film or coating.

摘要翻译： 将含硅聚合物如聚硅烷，聚（二苯基亚乙基亚苯基）和聚（二亚乙基亚乙炔基）与胺化合物混合，然后掺杂氧化掺杂剂，通常为碘和氯化铁，以产生具有改进的成型性的高导电性聚合物组合物。 通过旋涂可以容易地应用该组合物以形成高导电性膜或涂层。

公开(公告)号：US5537171A

公开(公告)日：1996-07-16

申请号：US320313

申请日：1994-10-11

申请人： Masanori Ogino ,  Yoshiaki Iwahara ,  Takeo Yamada ,  Shigeru Mori ,  Fumio Inoue ,  Akio Yamamoto

发明人： Masanori Ogino ,  Yoshiaki Iwahara ,  Takeo Yamada ,  Shigeru Mori ,  Fumio Inoue ,  Akio Yamamoto

IPC分类号： G03B21/14 ,  G03B21/62 ,  H04N9/31 ,  G03B21/00

CPC分类号： H04N9/3108 ,  G03B21/006 ,  G03B21/14 ,  G03B21/208 ,  G03B21/625 ,  H04N9/3155 ,  H04N9/3194

摘要： A liquid crystal projection display capable of functioning at a high light capturing efficiency and a high relative corner illuminance comprises a light source means including a light source, a liquid crystal panel means, a projection lens means and a screen means. A liquid lens formed by sealing a liquid in a space between opposite transparent members is disposed near the light source or the real image of the light source to enhance the relative corner illuminance without reducing the light capturing efficiency by multiplying the angle of divergence of light rays emitted by the light source by the reciprocal of the refractive index of the liquid. A first optical system disposed on the entrance side of the liquid crystal panel is provided with a relative corner illuminance enhancing means comprising a first light converging means disposed relatively near to the light source means, and a second light converging means disposed relatively remote from the light source means. The first light converging means enhances the relative corner illuminance on the entrance surface of the second light converging means.

摘要翻译： 能够以高的光捕获效率和高的相对角照度起作用的液晶投影显示器包括光源装置，其包括光源，液晶面板装置，投影透镜装置和屏幕装置。 通过在相对的透明构件之间的空间中密封液体而形成的液体透镜设置在光源附近或光源的实像附近，以通过将光线的发散角相乘来降低光捕获效率，从而提高相对的角度照度 由光源发射的液体的折射率的倒数。 设置在液晶面板的入口侧的第一光学系统设置有相对角照明增强装置，其包括相对靠近光源装置设置的第一聚光装置和相对远离光的第二聚光装置 源意味着。 第一聚光装置增强第二聚光装置的入射面上的相对角照度。

公开(公告)号：US5407987A

公开(公告)日：1995-04-18

申请号：US202627

申请日：1994-02-28

申请人： Motoo Fukushima ,  Eiichi Tabei ,  Shigeru Mori

发明人： Motoo Fukushima ,  Eiichi Tabei ,  Shigeru Mori

IPC分类号： C08G77/60 ,  H01B1/12 ,  C08K5/06

CPC分类号： C08G77/60 ,  H01B1/12

摘要： Polycyclic aromatic group-pendant polysilanes of the following general formula are described.[(R.sup.1 R.sup.2 Si).sub.k (R.sup.3 R.sup.4 Si).sub.m ].sub.nwherein R.sup.1, R.sup.2, R.sup.3, and R.sup.4 are, respectively, a hydrogen atom or a monovalent hydrocarbon group provided that at least one of R.sup.3 and R.sup.4 is a monovalent hydrocarbon group having a polycyclic aromatic group or a biphenyl group. When the polysilane is doped with an oxidative dopant, the polymer is rendered electrically conductive and has thus wide utility in various fields of photoconductive and electrically conductive materials without involving degradation of the polysilane.

摘要翻译： 描述了以下通式的多环芳基 - 侧基聚硅烷。 [（R 1 R 2 Si）k（R 3 R 4 Si）m] n其中R 1，R 2，R 3和R 4分别为氢原子或一价烃基，条件是R 3和R 4中的至少一个为具有多环芳香族的一价烃基 组或联苯基。 当聚硅烷掺杂有氧化掺杂剂时，聚合物变得具有导电性，因此在光导和导电材料的各个领域中具有广泛的用途，而不涉及聚硅烷的降解。