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    System and method to interleave memory
    61.
    发明授权
    System and method to interleave memory 有权
    用于交错内存的系统和方法

    公开(公告)号：US09208083B2

    公开(公告)日：2015-12-08

    申请号：US14169424

    申请日：2014-01-31

    Applicant: LSI Corporation

    Inventor： Yang Han ,  Zongwang Li ,  Shaohua Yang ,  Kaichi Zhang

    IPC: G06F12/00 ,  G06F12/06

    CPC classification number: G06F12/0607 ,  G11C7/1012 ,  G11C7/1042

    Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

    Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

    Systems and methods for enhanced data encoding and decoding
    62.
    发明授权
    Systems and methods for enhanced data encoding and decoding 有权
    用于增强数据编码和解码的系统和方法

    公开(公告)号：US09196299B2

    公开(公告)日：2015-11-24

    申请号：US14025104

    申请日：2013-09-12

    Applicant: LSI Corporation

    Inventor： Bruce A. Wilson ,  Shaohua Yang ,  Shu Li

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00

    CPC classification number: G11B20/1833 ,  G06F11/1076 ,  G11B2020/1853 ,  H03M13/00 ,  H03M13/1102 ,  H03M13/2909 ,  H03M13/293 ,  H03M13/41 ,  H03M13/6325 ,  H03M13/6343

    Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. As an example, a method is discussed that includes: applying a first level encoding on a section by section basis to a first data portion to yield a first encoding data including a first encoded portion; applying a second level encoding on a section by section basis to the first encoded portion to yield a first parity set; applying a third level encoding on a section by section basis to a combination of the first data portion, the second data portion, and a portion derived from the first encoded portion to yield a second encoding data.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于编码和解码信息的系统和方法。 作为示例，讨论了一种方法，其包括：将逐级编码应用于第一数据部分，以产生包括第一编码部分的第一编码数据; 对第一编码部分逐个应用第二级编码以产生第一奇偶校验集; 对于第一数据部分，第二数据部分和从第一编码部分导出的部分的组合，逐个应用第三级编码，以产生第二编码数据。

    Low density parity check decoder with dynamic scaling
    66.
    发明授权
    Low density parity check decoder with dynamic scaling 有权
    低密度奇偶校验解码器，动态缩放

    公开(公告)号：US09130589B2

    公开(公告)日：2015-09-08

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: G11B20/18 ,  H03M13/13 ,  H03M13/11 ,  H03M13/00 ,  H03M13/27

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

    Systems and methods for adjacent track interference based re-writing
    67.
    发明授权
    Systems and methods for adjacent track interference based re-writing 有权
    用于相邻轨道干扰重写的系统和方法

    公开(公告)号：US09099157B1

    公开(公告)日：2015-08-04

    申请号：US14268741

    申请日：2014-05-02

    Applicant: LSI Corporation

    Inventor： Eui Seok Hwang ,  Shaohua Yang

    IPC: G11B27/36 ,  G11B20/10 ,  G11B20/18

    CPC classification number: G11B20/10388 ,  G11B20/10305 ,  G11B20/10453 ,  G11B20/18

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for confirming data validity. In one case, a system is disclosed that includes an adjacent track interference confirmation circuit. The adjacent track interference confirmation circuit is operable to receive an indication of an adjacent track interference; determine a causal connection between the adjacent track interference and a mis-alignment of a read head and a track on a storage medium from which a data set corresponding to the indication of the adjacent track interference is derived; and provide a re-write signal where even after reduction of the mis-alignment the indication of adjacent track interference repeats.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于确认数据有效性的系统和方法。 在一种情况下，公开了一种包括相邻轨道干扰确认电路的系统。 相邻轨道干扰确认电路可操作以接收相邻轨道干扰的指示; 确定相邻轨道干涉之间的因果连接和读取头与存储介质上的轨道的错误对准，从该导体与轨道相应于相邻轨道干扰的指示得到的数据集; 并且提供重写信号，其中即使在减少对准后，相邻轨道干扰的指示重复。

    Systems and methods for multi-stage encoding of concatenated low density parity check codes
    70.
    发明授权
    Systems and methods for multi-stage encoding of concatenated low density parity check codes 有权
    连接低密度奇偶校验码的多级编码的系统和方法

    公开(公告)号：US09048873B2

    公开(公告)日：2015-06-02

    申请号：US13912079

    申请日：2013-06-06

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Yu Kou ,  Chung-Li Wang ,  Shaohua Yang ,  Shu Li

    IPC: H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1171 ,  H03M13/611 ,  H03M13/616

    Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

    Abstract translation: 数据编码系统包括数据编码器电路，其可操作以用低密度奇偶校验码矩阵的分量矩阵对多个数据扇区中的每一个进行编码，并产生输出码字。 数据编码器电路包括可用于计算和组合用于数据扇区的综合征的校正子计算电路。

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