公开(公告)号：US20080263383A1

公开(公告)日：2008-10-23

申请号：US12163493

申请日：2008-06-27

申请人： Daniel R. Knebel ,  William Robert Reohr ,  Li-Kong Wang

发明人： Daniel R. Knebel ,  William Robert Reohr ,  Li-Kong Wang

IPC分类号： G06F1/04

CPC分类号： G06F11/008

摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。

公开(公告)号：US20050282323A1

公开(公告)日：2005-12-22

申请号：US11202834

申请日：2005-08-12

申请人： Louis Hsu ,  Li-Kong Wang

发明人： Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L21/20 ,  H01L27/12 ,  D06N7/04 ,  G11B5/64 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/12 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02527 ,  Y10T428/12674 ,  Y10T428/24355 ,  Y10T428/24802 ,  Y10T428/24942 ,  Y10T428/30

摘要： A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.

摘要翻译： 提出了混合基板，即由不同材料制造的基板及其制造方法。 混合基板被配置为在其上制造两个以上的不同器件，具有高导热性，并且被配置用于在其上构图互连以互连在混合基板上制造的不同器件。

公开(公告)号：US06777286B2

公开(公告)日：2004-08-17

申请号：US10616243

申请日：2003-07-08

申请人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

发明人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

摘要翻译： 描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供 衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。 本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

公开(公告)号：US06504777B1

公开(公告)日：2003-01-07

申请号：US09924661

申请日：2001-08-08

申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/4094

摘要： In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanced capacitance resulting from a size difference of n-FET and p-FET latches in the sense amplifiers. An extra compensating capacitance Ce is added to the NCS node to adjust the loading capacitance to eliminate the bitline drifting.

摘要翻译： 在高密度动态存储器电路中，读出放大器由几个位线共享，以保持高密度和低功率设计。 然而，由于读出放大器中的n-FET和p-FET锁存器的大小差异导致的不平衡电容引起了几个周期的操作之后，位线均衡电平漂移。 一个额外的补偿电容Ce被添加到NCS节点以调整负载电容以消除位线漂移。

公开(公告)号：US06894916B2

公开(公告)日：2005-05-17

申请号：US10256715

申请日：2002-09-27

申请人： William Robert Reohr ,  Li-Kong Wang

发明人： William Robert Reohr ,  Li-Kong Wang

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C5/06

CPC分类号： G11C11/22

摘要： An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.

摘要翻译： 改进的非易失性存储器阵列包括多个存储器单元，至少一个存储器单元包括用于存储至少一个存储器单元的逻辑状态的三端非易失性存储元件。 存储器阵列还包括可操作地耦合到存储器单元的多个写入线，用于选择性地将存储器阵列中的一个或多个存储器单元的逻辑状态写入，并且可操作地耦合到存储器单元的多个位线和字线用于选择性地 读取和写入存储器阵列中的一个或多个存储器单元的逻辑状态。 有利地，存储器阵列被配置为消除对可操作地耦合到至少一个存储器单元中的对应的非易失性存储元件的通过栅极的需要。

公开(公告)号：US06823293B2

公开(公告)日：2004-11-23

申请号：US10334312

申请日：2002-12-31

申请人： Howard H. Chen ,  Louis Lu-Chen Hsu ,  Brian L. Ji ,  Li-Kong Wang

发明人： Howard H. Chen ,  Louis Lu-Chen Hsu ,  Brian L. Ji ,  Li-Kong Wang

IPC分类号： G06F1500

CPC分类号： G01R31/3004 ,  G01R31/31721

摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.

摘要翻译： 一种用于大规模集成电路的分层电源噪声监测装置和系统。 噪声监测装置是片上制造的，以测量芯片上的噪声。 噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。 噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。

公开(公告)号：US06426903B1

公开(公告)日：2002-07-30

申请号：US09923721

申请日：2001-08-07

申请人： Lawrence A. Clevenger ,  Louis Lu-Chen Hsu ,  Li-Kong Wang ,  Keith Kwong-Hon Wong

发明人： Lawrence A. Clevenger ,  Louis Lu-Chen Hsu ,  Li-Kong Wang ,  Keith Kwong-Hon Wong

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  Y10S977/888 ,  Y10S977/943

摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.

摘要翻译： 使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。 聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。 反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。

公开(公告)号：US06389505B1

公开(公告)日：2002-05-14

申请号：US09196086

申请日：1998-11-19

申请人： Philip George Emma ,  William Robert Reohr ,  Li-Kong Wang

发明人： Philip George Emma ,  William Robert Reohr ,  Li-Kong Wang

IPC分类号： G06F1200

CPC分类号： G06F12/0893 ,  G06F12/0802

摘要： A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.

摘要翻译： 一种用于通过仅恢复在分配的数据保留时间内未被读取或写入的那些单元来减少维持DRAM中的数据所需的刷新动作数量的系统和方法。 一个实施例描述了应用于DRAM高速缓存的还原跟踪系统。 还原跟踪系统可以替代地应用于具有信息重复的任何存储器架构。 例如，可以通过记录和更新DRAM中的一个或多个数据条目的刷新状态来减少维护DRAM中的数据条目所需的刷新动作的数量; 并使那些具有过期状态的数据条目无效。 因此，可以使更多的存储器带宽可用于计算机系统。

公开(公告)号：US08495444B2

公开(公告)日：2013-07-23

申请号：US12163493

申请日：2008-06-27

申请人： Daniel R. Knebel ,  William Robert Reohr ,  Li-Kong Wang

发明人： Daniel R. Knebel ,  William Robert Reohr ,  Li-Kong Wang

IPC分类号： G01R31/30

CPC分类号： G06F11/008

摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

公开(公告)号：US07475320B2

公开(公告)日：2009-01-06

申请号：US10643549

申请日：2003-08-19

申请人： Daniel R. Knebel ,  William Robert Reohr ,  Li-Kong Wang

发明人： Daniel R. Knebel ,  William Robert Reohr ,  Li-Kong Wang

IPC分类号： G06F11/32 ,  G06F11/18

CPC分类号： G06F11/008

摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。