公开(公告)号：US09508409B2

公开(公告)日：2016-11-29

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US20140219043A1

公开(公告)日：2014-08-07

申请号：US13758667

申请日：2013-02-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William F. Jones ,  Jeffrey P. Wright

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4087 ,  G11C17/16 ,  G11C17/18 ,  G11C29/783 ,  G11C2211/4068

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Abstract translation: 本文公开了用于目标行刷新的装置和方法。 在示例性装置中，预解码器接收目标行地址并确定与目标行地址相关联的目标行存储器是主存储器还是冗余存储器行。 如果主行是目标行或物理上邻近待刷新的存储器的行，存储器的一行或多行存储器将被刷新，则预解码器还被配置为使物理上邻近主行存储器的一行或多行存储器被刷新，如果 内存冗余行是目标行内存。