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    Thermally optimized phase change memory cells and methods of fabricating the same
    61.
    发明授权
    Thermally optimized phase change memory cells and methods of fabricating the same 有权

    公开(公告)号：US10305036B2

    公开(公告)日：2019-05-28

    申请号：US15994815

    申请日：2018-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.

    Memory cell architecture for multilevel cell programming
    63.
    发明授权
    Memory cell architecture for multilevel cell programming 有权

    公开(公告)号：US10049737B2

    公开(公告)日：2018-08-14

    申请号：US15433881

    申请日：2017-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Mario Allegra ,  Mattia Boniardi

    IPC: G11C16/06 ,  G11C13/00 ,  G11C11/56

    Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.

    Memory Arrays and Methods of Forming Memory Arrays
    67.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权

    公开(公告)号：US20170148852A1

    公开(公告)日：2017-05-25

    申请号：US15421855

    申请日：2017-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

    Memory Arrays and Methods of Forming Memory Arrays
    68.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权

    公开(公告)号：US20160190443A1

    公开(公告)日：2016-06-30

    申请号：US15064002

    申请日：2016-03-08

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

    Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

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