公开(公告)号：US20230067814A1

公开(公告)日：2023-03-02

申请号：US17447505

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Paolo Tessariol

IPC: H01L21/768 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method of forming a microelectronic device comprises forming a stack structure over a source structure, forming pillar structures vertically extending through the stack structure, and forming at least one trench vertically extending through the stack structure. The at least one trench defines at least one stadium structure comprising opposing stair step structures having steps comprising horizontal ends of tiers. Additional trenches may be formed to vertically extend through the stack structure, and at least one further trench may be formed to vertically extend through the stack structure. The at least one further trench defines at least one additional stadium structure comprising additional opposing stair step structures having additional steps comprising additional horizontal ends of the tiers. A dielectric material may be formed within the at least one trench, the additional trenches, and the at least one further trench. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20230031083A1

公开(公告)日：2023-02-02

申请号：US17966619

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Qiang Tang

IPC: H01L49/02 ,  H01L27/112 ,  H01L23/535 ,  H01L21/768 ,  H01L23/522

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.

公开(公告)号：US11563022B2

公开(公告)日：2023-01-24

申请号：US16550252

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US11557341B2

公开(公告)日：2023-01-17

申请号：US17011018

申请日：2020-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

公开(公告)号：US11489038B2

公开(公告)日：2022-11-01

申请号：US15689735

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Qiang Tang

IPC: H01L49/02 ,  H01L27/112 ,  H01L23/535 ,  H01L21/768 ,  H01L23/522

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.

公开(公告)号：US11424267B2

公开(公告)日：2022-08-23

申请号：US17121441

申请日：2020-12-14

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Yoshiaki Fukuzumi

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: In an example of forming a stacked memory array, a stack of alternating first and second dielectrics is formed. A dielectric extension is formed through the stack such that a first portion of the dielectric extension is in a first region of the stack between a first group of semiconductor structures and a second group of semiconductor structures in a second region of the stack and a second portion of the dielectric extension extends into a third region of the stack that does not include the first and second semiconductor structures. An opening is formed through the first region, while the dielectric extension couples the alternating first and second dielectrics in the third region to the alternating first and second dielectrics in the second region.

公开(公告)号：US20220230960A1

公开(公告)日：2022-07-21

申请号：US17658404

申请日：2022-04-07

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Jian Li ,  Graham R. Wolstenholme ,  Paolo Tessariol ,  George Matamis ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

公开(公告)号：US11271002B2

公开(公告)日：2022-03-08

申请号：US16382932

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US20220059559A1

公开(公告)日：2022-02-24

申请号：US17000754

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US20210151375A1

公开(公告)日：2021-05-20

申请号：US17134930

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.