公开(公告)号：US20140040683A1

公开(公告)日：2014-02-06

申请号：US14045830

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung S. Hoei

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/1068 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3495 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract translation: 在一个或多个所公开的实施例中，存储器装置中的存储器单元在疲劳状况的指示时被刷新。 在一个这样的实施例中，控制器监视单元的行为参数，并且确定是否有任何参数在每个参数设置的正常范围之外，从而指示疲劳状况。 如果任何细胞表示疲劳状况，来自指示疲劳的细胞块的数据被移动到另一个块。 在一个实施例中，在写入另一个存储块之前对数据执行错误检测和校正处理。

公开(公告)号：US08578244B2

公开(公告)日：2013-11-05

申请号：US13633158

申请日：2012-10-02

Applicant: Micron Technology, Inc

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung S. Hoei

IPC: G11C29/00 ,  G11C5/14 ,  H03M13/00 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G06F11/1072 ,  G11C29/12005

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract translation: 在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。 编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。 如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

公开(公告)号：US20130286745A1

公开(公告)日：2013-10-31

申请号：US13929319

申请日：2013-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Frankie Roohparvar ,  Vishal Sarin ,  William Radke

IPC: G11C29/04

CPC classification number: H03M13/23 ,  G06F11/1068 ,  G11C16/26 ,  G11C29/04

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).

Abstract translation: 公开了诸如涉及包括存储器单元阵列的闪速存储器件的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。 例如，维特比算法可用于补充纠错码（ECC）。