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公开(公告)号：US20190206485A1
公开(公告)日：2019-07-04
申请号：US16298313
申请日：2019-03-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.
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公开(公告)号：US20180322922A1
公开(公告)日：2018-11-08
申请号：US16019650
申请日：2018-06-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luca De Santis , Tommaso Vali , Kenneth J. Eldredge , Vishal Sarin
CPC classification number: G11C15/046 , G11C16/0483 , G11C16/10 , G11C29/52
Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
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公开(公告)号：US09858991B2
公开(公告)日：2018-01-02
申请号：US15287956
申请日：2016-10-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
CPC classification number: G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.
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公开(公告)号：US09197251B2
公开(公告)日：2015-11-24
申请号：US14245662
申请日：2014-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.
Abstract translation: 公开了与诸如包括存储器单元阵列的闪存器件的存储器件有关的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。
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公开(公告)号：US20140237326A1
公开(公告)日：2014-08-21
申请号：US14245662
申请日：2014-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).
Abstract translation: 公开了诸如涉及包括存储器单元阵列的闪速存储器件的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。 例如，维特比算法可用于补充纠错码（ECC）。
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Patent Agency Ranking
公开(公告)号：US08719680B2
公开(公告)日：2014-05-06
申请号：US13929319
申请日：2013-06-27
Applicant: Micron Technology, Inc.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.
Abstract translation: 公开了与诸如包括存储器单元阵列的闪存器件的存储器件有关的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。
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7.发明授权Analog sensing of memory cells with a source follower driver in a semiconductor memory device 有权在半导体存储器件中用源极跟随器驱动器对存储器单元进行模拟感测公开(公告)号：US08687430B2
公开(公告)日：2014-04-01
申请号：US13919350
申请日：2013-06-17
Applicant: Micron Technology, Inc.
Inventor： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC: G11C16/06
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C16/3481 , G11C27/02 , G11C27/024 , G11C2211/5634
Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
Abstract translation: 公开了存储器件，方法和采样和保持电路，包括包括耦合到位线的采样和保持电路的存储器件。 一个这样的采样和保持电路包括读取电路，验证电路和参考电路。 读取电路存储从所选存储单元读取的读取阈值电压。 验证电路存储与读取的阈值电压相比较的目标阈值电压，以在目标和读取阈值电压基本相等时产生禁止信号。 参考电路存储参考阈值电压，该参考阈值电压可用于转换读取阈值电压以补偿晶体管电压降和/或温度变化。
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8.发明申请PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL 有权将错误修正代码编入固态状态存储器件，其中每个单元有不同的位数公开(公告)号：US20140053033A1
公开(公告)日：2014-02-20
申请号：US14056031
申请日：2013-10-17
Applicant: Micron Technology, Inc.
Inventor： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
CPC classification number: G06F11/1076 , G06F11/1072 , G11C29/12005
Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
Abstract translation: 在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。 编程错误校正码（ECC）和元数据到这样的存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。 如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。
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公开(公告)号：US20130301357A1
公开(公告)日：2013-11-14
申请号：US13943254
申请日：2013-07-16
Applicant: Micron Technology, Inc.
Inventor： Vishal Sarin , Frankie Roohpavar , Hoei Jung Sheng
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/3418
Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
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公开(公告)号：US08582357B2
公开(公告)日：2013-11-12
申请号：US13736179
申请日：2013-01-08
Applicant: Micron Technology, Inc.
Inventor： Vishal Sarin
IPC: G11C11/34
CPC classification number: G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
Abstract: The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential.
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