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公开(公告)号：US09093162B2
公开(公告)日：2015-07-28
申请号：US14046640
申请日：2013-10-04
Applicant: Micron Technology, Inc.
Inventor： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar , Giulio-Giuseppe Marotta
CPC classification number: G11C16/12 , G11C7/16 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5621 , G11C2211/5634 , G11C2211/5642
Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.
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公开(公告)号：US09025388B2
公开(公告)日：2015-05-05
申请号：US14045492
申请日：2013-10-03
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC: G11C16/04 , G11C16/10 , G11C11/56 , G11C16/34 , G11C11/404
CPC classification number: G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US20130286745A1
公开(公告)日：2013-10-31
申请号：US13929319
申请日：2013-06-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
IPC: G11C29/04
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).
Abstract translation: 公开了诸如涉及包括存储器单元阵列的闪速存储器件的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。 例如，维特比算法可用于补充纠错码（ECC）。
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Patent Agency Ranking
公开(公告)号：US20140098607A1
公开(公告)日：2014-04-10
申请号：US14046640
申请日：2013-10-04
Applicant: Micron Technology, Inc.
Inventor： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar , Giulio-Giuseppe Marotta
IPC: G11C16/12
CPC classification number: G11C16/12 , G11C7/16 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5621 , G11C2211/5634 , G11C2211/5642
Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.
Abstract translation: 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将斜波电压施加到存储器单元的控制栅极和模数转换器（ADC）。 上述方法的实施例还包括响应于斜坡电压何时使存储器单元跳闸感测电路至少部分地检测ADC的输出。
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公开(公告)号：US09197251B2
公开(公告)日：2015-11-24
申请号：US14245662
申请日：2014-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.
Abstract translation: 公开了与诸如包括存储器单元阵列的闪存器件的存储器件有关的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。
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公开(公告)号：US20140237326A1
公开(公告)日：2014-08-21
申请号：US14245662
申请日：2014-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).
Abstract translation: 公开了诸如涉及包括存储器单元阵列的闪速存储器件的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。 例如，维特比算法可用于补充纠错码（ECC）。
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公开(公告)号：US08719680B2
公开(公告)日：2014-05-06
申请号：US13929319
申请日：2013-06-27
Applicant: Micron Technology, Inc.
Inventor： Frankie Roohparvar , Vishal Sarin , William Radke
CPC classification number: H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.
Abstract translation: 公开了与诸如包括存储器单元阵列的闪存器件的存储器件有关的方法和装置。 一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。 该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。 在一个实施例中，闪存单元阵列包括字线和位线。 检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。 维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。
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公开(公告)号：US20140043912A1
公开(公告)日：2014-02-13
申请号：US14045492
申请日：2013-10-03
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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