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公开(公告)号：US20090111228A1
公开(公告)日：2009-04-30
申请号：US11924073
申请日：2007-10-25
IPC分类号： H01L21/33
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译： 本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在 最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。
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公开(公告)号：US07485487B1
公开(公告)日：2009-02-03
申请号：US11970207
申请日：2008-01-07
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the metal stud to expose a sidewall of the via; etching the sidewall of the via in the first dielectric layer with a isotropic etch step to produce an undercut region extending beneath a portion of the second dielectric layer; forming a conformal insulating layer on at least the portion of the second dielectric layer overlying the undercut region to provide a keyhole; etching the conformal insulating layer with an anisotropic etch to provide a collar that exposes the metal stud; forming a barrier metal within the collar in contact with the metal stud; and forming a phase change material in contact with the barrier metal.
摘要翻译： 本发明在一个实施例中提供了一种形成存储器件的方法，该存储器件包括：提供包括至少一个通孔的第一介电层，所述通孔包含金属螺柱; 在所述第一电介质层的顶部提供第二电介质层; 使金属螺柱凹陷以暴露通孔的侧壁; 用各向同性蚀刻步骤蚀刻第一介电层中的通孔的侧壁，以产生在第二介电层的一部分下方延伸的底切区域; 在覆盖所述底切区域的所述第二介电层的至少一部分上形成保形绝缘层以提供锁眼; 用各向异性蚀刻蚀刻保形绝缘层以提供露出金属螺柱的套环; 在所述套环内形成与所述金属螺栓接触的阻挡金属; 并形成与阻挡金属接触的相变材料。
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公开(公告)号：US08633464B2
公开(公告)日：2014-01-21
申请号：US13350967
申请日：2012-01-16
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译： 一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面 沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面 每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极 。
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公开(公告)号：US08518718B2
公开(公告)日：2013-08-27
申请号：US13613313
申请日：2012-09-13
IPC分类号： H01L21/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675
摘要： A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
摘要翻译： 一种用于形成存储器件的方法包括：形成具有在衬底中具有波状轮廓的内表面的空腔，在所述空腔中沉积铁磁材料，在所述衬底上形成接近所述铁磁材料的一部分的读取元件，以及形成 在基板上的写入元件靠近铁磁材料的第二部分。
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公开(公告)号：US08467221B2
公开(公告)日：2013-06-18
申请号：US12833446
申请日：2010-07-09
IPC分类号： G11C19/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675
摘要： A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
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66.发明申请BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS 有权无边界自对准的金属接触方式使用可印制的电介质材料公开(公告)号：US20130087860A1
公开(公告)日：2013-04-11
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译： 无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。 示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。 该方法还包括在封闭区域内沉积金属层。 这样形成的金属触点与封闭区域自对准。
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公开(公告)号：US20130087756A1
公开(公告)日：2013-04-11
申请号：US13268151
申请日：2011-10-07
CPC分类号： H01L45/1246 , H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner.
摘要翻译： 存储单元结构和形成这种结构的方法。 示例性存储单元包括形成在衬底内的底部电极。 存储单元还包括与底部电极接触的相变存储元件。 存储单元包括横向围绕相变存储元件的衬垫。 衬垫包括导热并电绝缘的电介质材料。 存储单元包括横向围绕衬垫的绝缘介电层。 绝缘介电层包括具有比衬里更低导热性的材料。
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公开(公告)号：US08344351B2
公开(公告)日：2013-01-01
申请号：US13159594
申请日：2011-06-14
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A phase change memory device includes a plurality of memory cells comprising a substrate having a contact surface with an array of conductive contacts to be connected with access circuitry and a nitride layer formed at the contact surface. A plurality of vias are formed through the nitride layer to the contact surface and correspond to each conductive contact, the vias including a conformal conductive seed layer lining each via along exposed portions of the nitride layer and the contact surface and having oxidized edges. A dielectric layer is recessed within the conformal conductive seed layer and exposes a center region of each via. A phase change material is recessed within the center region of each via. A conductive material that remains conductive upon oxidation is formed over the phase change material. A top electrode is formed on each memory cell.
摘要翻译： 相变存储器件包括多个存储单元，其包括具有与要与接触电路连接的导电触点阵列的接触表面的衬底和在接触表面形成的氮化物层。 多个通孔通过氮化物层形成到接触表面并且对应于每个导电接触，通孔包括沿着氮化物层和接触表面的暴露部分并且具有氧化边缘的每个通孔衬里的共形导电种子层。 电介质层凹入保形导电晶种层内并露出每个通孔的中心区域。 相变材料凹陷在每个通孔的中心区域内。 在相变材料上形成氧化时保持导电的导电材料。 在每个存储单元上形成顶部电极。
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公开(公告)号：US20120318649A1
公开(公告)日：2012-12-20
申请号：US13164126
申请日：2011-06-20
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H57/00 , H01L21/285
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction.
摘要翻译： 公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。 该方法包括提供设置在设置在硅衬底上的绝缘层上的硅层; 从所述绝缘层释放所述硅层的一部分，使得其至少部分地悬挂在所述绝缘层中的空腔上; 在至少所述硅层的释放部分的至少一个表面上沉积金属（例如Pt），并且使用热处理，使用沉积的金属至少完全硅化硅层的释放部分。 当整个Si元件被硅化时，该方法消除了对释放的Si元件的硅化物引起的应力。 此外，在形成完全硅化材料之后，也不使用常规的湿化学蚀刻，从而减少引起硅化物腐蚀和粘性增加的可能性。
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公开(公告)号：US07960203B2
公开(公告)日：2011-06-14
申请号：US12021577
申请日：2008-01-29
IPC分类号： H01L21/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。
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