公开(公告)号：US20100276743A1

公开(公告)日：2010-11-04

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理，以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US20100118610A1

公开(公告)日：2010-05-13

申请号：US12610703

申请日：2009-11-02

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A stacked body with a plurality of dielectric films and electrode films alternately stacked therein is provided. The electrode film is divided into a plurality of control gate electrodes extending in one direction. The stacked body is provided with a U-pillar penetrating through the select gate electrodes and the control gate electrodes, having one end connected to a source line, and having the other end connected to a bit line. Moreover, a different potential is applied to uppermost one of the control gate electrodes than that applied to the other control gate electrodes.

摘要翻译： 提供了具有交替层叠的多个电介质膜和电极膜的层叠体。 电极膜被分成沿一个方向延伸的多个控制栅电极。 层叠体设置有穿过选择栅极和控制栅电极的U柱，其一端连接到源极线，并且另一端连接到位线。 此外，与施加到其他控制栅电极相比，控制栅电极的最上一个施加不同的电位。

公开(公告)号：US20100038699A1

公开(公告)日：2010-02-18

申请号：US12542276

申请日：2009-08-17

申请人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.

摘要翻译： 通过交替堆叠多个绝缘膜和多个电极膜，在硅基板上形成层叠体，并且形成贯通孔，以在层叠方向上延伸。 接下来，通过通孔蚀刻绝缘膜，在电极膜之间形成间隙。 电荷存储层沿着通孔的侧面和间隙的内表面形成，硅柱填充到通孔中。 由此，制造非易失性半导体存储器件。

公开(公告)号：US20100034028A1

公开(公告)日：2010-02-11

申请号：US12536226

申请日：2009-08-05

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： G11C7/00 ,  G11C16/02 ,  G11C16/26

CPC分类号： H01L27/11578 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line side of a memory cell of the number k (k is an integer of 1 to (n−1)) as counted from an end on a bit line side in a selected semiconductor pillar, positive program potential is given to the electrode film of the number 1 to k as counted from the bit line side, and 0 V is given to the electrode film of the number (k+1) to n, therewith positive potential is given to the bit line and 0 V is given to the source line.

摘要翻译： 在具有n（n为2以上的整数）的电极膜的非易失性半导体存储装置中，在各电极膜的上下配置有电荷存储层的情况下，在将数据“0”注入到电荷存储部 在选择的半导体柱中从位线侧的端部开始计数k（k为1〜（n-1）的整数）的存储单元的源极侧的层，将正的程序电位赋予 从位线侧计数1〜k的电极膜，向数字（k + 1）〜n的电极膜施加0V，其中给定位线为0V，0V为 给源线。

公开(公告)号：US08884355B2

公开(公告)日：2014-11-11

申请号：US12727712

申请日：2010-03-19

申请人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/72 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件包括：堆叠结构单元，包括多个电极膜和沿第一方向交替堆叠的多个电极间绝缘膜; 第一选择栅电极，沿第一方向堆叠在层叠结构单元上; 第一半导体柱在第一方向上穿透层叠结构单元和第一选择栅电极; 设置在每个电极膜和第一半导体柱的交点处的第一存储单元; 以及设置在所述第一半导体柱和所述第一选择栅极之间的第一选择栅极绝缘膜，所述第一选择栅电极包括设置在所述第一选择栅电极的与所述第一方向垂直的面上的第一硅化物层。

公开(公告)号：US08541866B2

公开(公告)日：2013-09-24

申请号：US12722920

申请日：2010-03-12

申请人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Tomoko Fujiwara

发明人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Tomoko Fujiwara

IPC分类号： H01L29/00

CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括沿第一方向堆叠的多个堆叠的元件单元，每个堆叠元件单元包括由垂直于第一元件垂直设置的第一导电类型的半导体制成的第一导电膜 方向和与第一导电膜在第一方向上堆叠的第一绝缘膜; 所述半导体柱在所述第一方向上穿透所述层叠结构单元，并且包括第二导电类型的导电区域，所述半导体柱包括与所述第一导电膜相对的第一区域，以及设置在所述第一区域之间的第二区域， 所述第一方向，所述第二区域具有与所述第一区域的电阻不同的电阻; 以及设置在所述半导体柱和所述第一导电膜之间的第二绝缘膜。

公开(公告)号：US08436415B2

公开(公告)日：2013-05-07

申请号：US12723981

申请日：2010-03-15

申请人： Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.

摘要翻译： 存储器串包括：第一半导体层，包括在基板上沿堆叠方向延伸的柱状部分; 围绕所述柱状部分的第一电荷存储层; 以及堆叠在所述基板上以围绕所述第一电荷存储层的多个第一导电层。 选择晶体管包括：与柱状部分的上表面接触并沿堆叠方向延伸的第二半导体层; 围绕所述第二半导体层的第二电荷存储层; 以及沉积在所述第一导电层上方以围绕所述第二电荷存储层的第二导电层。 第二电荷存储层由第二导电层向下的层向第二导电层的上端附近形成，并且不形成在上端附近的上方。

公开(公告)号：US08374033B2

公开(公告)日：2013-02-12

申请号：US12728694

申请日：2010-03-22

申请人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3413 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括多层结构，其包括沿第一方向交替堆叠的电极膜和电极间绝缘膜; 在所述第一方向上穿透所述多层结构的半导体柱; 设置在所述半导体柱和所述电极膜之间的存储层; 设置在所述存储层和所述半导体柱之间的内部绝缘膜; 设置在存储层和电极膜之间的外部绝缘膜; 以及电连接到第一半导体柱的布线。 在擦除操作中，控制单元将第一布线设置在第一电位，并将电极膜设置在比第一电位低的第二电位，然后将第一布线设置在第三电位，并将电极膜设置为高于第四电位 比第三个潜力。

公开(公告)号：US08338876B2

公开(公告)日：2012-12-25

申请号：US12555320

申请日：2009-09-08

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L29/788

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US08264031B2

公开(公告)日：2012-09-11

申请号：US12696544

申请日：2010-01-29

申请人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

发明人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film. The fourth insulating film is provided between the semiconductor pillar and the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 多层结构; 半导体柱; 第三绝缘膜; 和第四绝缘膜层。 多层结构设置在半导体衬底上，并且包括沿垂直于半导体衬底的主表面的第一方向堆叠的多个构成层叠体。 多个构成多层体中的每一个包括平行于主表面设置的电极膜，第一绝缘膜，设置在电极膜和第一绝缘膜之间的电荷存储层，以及设置在电荷存储层 和电极膜。 半导体柱沿第一方向穿透多层结构。 第三绝缘膜设置在半导体柱和电极膜之间。 第四绝缘膜设置在半导体柱和电荷存储层之间。