公开(公告)号：US06643604B1

公开(公告)日：2003-11-04

申请号：US09608091

申请日：2000-06-30

申请人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan

IPC分类号： G01K100

CPC分类号： H01L21/67115

摘要： A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of lamps and optical fibers, each optical fiber directing radiation to and heating a respective portions of a bakeplate on which the material is to be placed. In one embodiment, the temperature at various locations on the material placed on the bakeplate is determined and the heating rates are controlled in response to those measurements. In another aspect of the invention, the temperature at various portions of the bakeplate is determined and controlled. In this latter aspect, uniform heating of the material is a consequence of uniform bakeplate temperature.

摘要翻译： 提供了用于调节材料的加热温度的系统。 该材料可以是例如光致抗蚀剂，顶部或底部抗反射涂层，低K电介质材料，SOG或其它旋涂材料。 该系统包括多个灯和光纤，每个光纤将辐射引导到其上放置材料的面板的相应部分并加热。 在一个实施例中，确定放置在面板上的材料上的各个位置处的温度，并响应于这些测量来控制加热速率。 在本发明的另一方面中，确定并控制了木板的不同部分的温度。 在后一方面，材料的均匀加热是均匀烘烤温度的结果。

公开(公告)号：US06573498B1

公开(公告)日：2003-06-03

申请号：US09608096

申请日：2000-06-30

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi Phan ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi Phan ,  Michael K. Templeton

IPC分类号： G01N2300

CPC分类号： G01N23/225 ,  H01J2237/2826

摘要： The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature and correlating the electrical measurement with an SEM measurement thereof. The correlation of the electrical and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature. A processor is provided to correlate the optical and electrical measurements of the reference sample feature, whereby a reference feature CD is obtained. The system may further correlate workpiece feature measurements with the reference feature CD in order to determine or obtain a workpiece feature CD.

摘要翻译： 本发明涉及一种用于校准扫描电子显微镜（SEM）的系统和方法。 该方法包括测量校准标准参考样本特征的电特性并将电测量与其SEM测量相关联。 电和SEM测量的相关性为参考样品特征提供了临界尺寸（CD），然后可以将其用于关联工件特征的SEM测量。 该系统提供具有电连接到探针的可测量特征的参考样本。 探头提供参考样品特征的电气测量。 该系统还包括适于提供参考样品特征的光学测量的扫描电子显微镜（SEM）。 提供处理器以使参考样本特征的光学和电学测量相关，由此获得参考特征CD。 该系统可以进一步将工件特征测量与参考特征CD相关联，以便确定或获得工件特征CD。

公开(公告)号：US06573497B1

公开(公告)日：2003-06-03

申请号：US09607628

申请日：2000-06-30

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi Phan ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi Phan ,  Michael K. Templeton

IPC分类号： G01R3126

CPC分类号： H01J37/265 ,  H01J37/244 ,  H01J2237/24564 ,  H01J2237/2803 ,  H01J2237/2817 ,  H01J2237/2826

摘要： The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature via a current induced by an electron beam (e-beam) and correlating the e-beam induced current measurement with an SEM measurement thereof. The correlation of the e-beam induced current and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature based on an e-beam induced current. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature and workpiece features. A processor is provided to correlate the optical and e-beam induced current measurements of the reference sample feature, whereby a reference feature CD is obtained. The system may further correlate workpiece feature measurements with the reference feature CD in order to determine or obtain a workpiece feature CD.

摘要翻译： 本发明涉及一种用于校准扫描电子显微镜（SEM）的系统和方法。 该方法包括通过由电子束（电子束）感应的电流测量校准标准参考样本特征的电特性，并将电子束感应电流测量与其SEM测量相关联。 电子束感应电流和SEM测量的相关性为参考样品特征提供了临界尺寸（CD），然后可以将其用于关联工件特征的SEM测量。 该系统提供具有电连接到探针的可测量特征的参考样本。 探针基于电子束感应电流提供参考样品特征的电测量。 该系统还包括适于提供参考样品特征和工件特征的光学测量的扫描电子显微镜（SEM）。 提供处理器以使参考样本特征的光束和电子束感应电流测量值相关，从而获得参考特征CD。 该系统可以进一步将工件特征测量与参考特征CD相关联，以便确定或获得工件特征CD。

公开(公告)号：US06541184B1

公开(公告)日：2003-04-01

申请号：US09655979

申请日：2000-09-06

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur

IPC分类号： G03C556

CPC分类号： H01L21/6715 ,  G03F7/3028

摘要： A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied. The thickness uniformity data can also be used to adjust the volume of developer applied along the path and/or the volume flow rate.

摘要翻译： 提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。 该系统包括多个尖端喷嘴和运动系统，该运动系统将喷嘴移动到位于基板上的光致抗蚀剂材料层的中心区域上方的操作位置，并且当喷嘴扫描移动穿过预定路径时施加一定体积的显影剂。 移动系统通过提供具有第一臂构件的臂来移动喷嘴，该臂具有可围绕第一旋转轴线枢转的第一臂构件和可围绕第二旋转轴线枢转或可沿着平移轴线移动的第二臂构件。 该系统还提供了测量设置在测试晶片上的显影的光致抗蚀剂材料层的厚度均匀性的测量系统。 当施加显影剂时，厚度均匀性数据用于重新配置喷嘴的预定路径。 厚度均匀性数据也可用于调节沿路径施加的显影剂的体积和/或体积流量。

公开(公告)号：US06513996B1

公开(公告)日：2003-02-04

申请号：US10050436

申请日：2002-01-16

申请人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03B500

CPC分类号： G03F7/3021

摘要： One aspect of the present invention relates to a method and an apparatus for rinsing a substrate during a development process to mitigate pattern collapse. The apparatus includes a bath chamber; a substrate holder disposed in the bath chamber for holding the substrate having a resist pattern formed thereon; a first nozzle for dispensing a first rinsing solution having a first density and first surface tension into the bath chamber; a second nozzle for dispensing a second rinsing solution having a second density and second surface tension, which is less than the first rinsing solution, into the bath chamber; a drain disposed in a bottom portion of the bath chamber; and a controlling system operatively coupled to the first nozzle, the second nozzle and the drain designed to regulate and coordinate the operation of the first nozzle, the second nozzle and the drain.

摘要翻译： 本发明的一个方面涉及一种用于在显影过程中漂洗衬底以减轻图案崩溃的方法和装置。 该装置包括浴室; 设置在所述浴室中用于保持形成有抗蚀剂图案的所述基板的基板保持架; 用于将具有第一密度和第一表面张力的第一冲洗溶液分配到所述浴室中的第一喷嘴; 第二喷嘴，用于将具有小于第一冲洗溶液的第二密度和第二表面张力的第二冲洗溶液分配到浴室中; 排水口，其设置在所述浴室的底部; 以及可操作地联接到第一喷嘴，第二喷嘴和排水口的设计用于调节和协调第一喷嘴，第二喷嘴和排水管的操作的控制系统。

公开(公告)号：US06455416B1

公开(公告)日：2002-09-24

申请号：US09706967

申请日：2000-11-06

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  G03F7/091 ,  H01L21/31144

摘要： One aspect of the present invention relates to a method of processing a semiconductor structure, involving the steps of providing a substrate having an insulation layer thereover; forming a first antireflection coating over the insulation layer; patterning a first resist over the antireflection coating; forming a plurality of vias in the insulation layer and the first antireflection coating, the vias having a first width; filling the via with a second antireflection coating, the second antireflection coating comprising a dye and a film forming material; patterning a second resist over the structure and removing the second antireflection coating from the via; forming a trench over the plurality of vias in the insulation layer, the trench having a width that is larger than the average width of the vias; and filling the trench and vias with a conductive material. The present invention provides improved dual damascene methods for substrates by using a developer soluble ARC containing a dye to facilitate the formation of trenches directly over the previously formed vias.

摘要翻译： 本发明的一个方面涉及一种处理半导体结构的方法，包括以下步骤：提供其上具有绝缘层的基板; 在所述绝缘层上形成第一抗反射涂层; 在抗反射涂层上图案化第一抗蚀剂; 在所述绝缘层和所述第一抗反射涂层中形成多个通孔，所述通孔具有第一宽度; 用第二抗反射涂层填充通孔，第二抗反射涂层包含染料和成膜材料; 在所述结构上形成第二抗蚀剂并从所述通孔去除所述第二抗反射涂层; 在所述绝缘层中的多个通孔上形成沟槽，所述沟槽的宽度大于所述通孔的平均宽度; 并用导电材料填充沟槽和通孔。 本发明通过使用含有染料的显影剂可溶性ARC来促进直接在先前形成的通孔上形成沟槽，从而为衬底提供改进的双镶嵌方法。

公开(公告)号：US06451512B1

公开(公告)日：2002-09-17

申请号：US09565691

申请日：2000-05-01

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC分类号： G03F700

CPC分类号： G03F7/265 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： In one embodiment, the present invention relates to a method of processing an ultrathin resist, involving the steps of depositing the ultra-thin photoresist over a semiconductor substrate, the ultra-thin resist having a thickness less than about 3,000 Å; irradiating the ultra-thin resist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin resist; and contacting the ultra-thin resist with a silicon containing compound in an environment of at least one of ultraviolet light and ozone, wherein contact of the ultra-thin resist with the silicon containing compound is conducted between irradiating and developing the ultra-thin resist or after developing the ultra-thin resist.

摘要翻译： 在一个实施方案中，本发明涉及一种处理超薄抗蚀剂的方法，包括以下步骤：在半导体衬底上沉积超薄光致抗蚀剂，超薄抗蚀剂的厚度小于约; 用波长约250nm或更小的电磁辐射照射超薄抗蚀剂; 开发超薄抗蚀剂; 以及在紫外光和臭氧中的至少一种的环境下使超薄抗蚀剂与含硅化合物接触，其中超薄抗蚀剂与含硅化合物的接触在照射和显影超薄抗蚀剂之间进行，或 在开发超薄抗蚀剂后。

公开(公告)号：US06329124B1

公开(公告)日：2001-12-11

申请号：US09320417

申请日：1999-05-26

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton

IPC分类号： G03F726

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086

摘要： The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. An ARC layer under the photoresist layer is etched. A nitride layer is formed to be conformal to the patterned ARC layer and exposed portions of an underlayer underying the patterned ARC layer. The nitride layer is etched to form nitride sidewalls, the nitride sidewalls reducing the smallest space dimension of the exposed underlayer area to d2, wherein d2

摘要翻译： 本发明涉及一种形成蚀刻掩模的方法。 图案化光致抗蚀剂层，其中d1是光致抗蚀剂层下面的层的暴露区域的最小空间尺寸。 蚀刻光刻胶层下方的ARC层。 氮化物层形成为与图案化的ARC层一致，并且曝光部分的底层在图案化的ARC层下面。 蚀刻氮化物层以形成氮化物侧壁，氮化物侧壁将暴露的底层区域的最小空间尺寸减小到d2，其中d2

公开(公告)号：US06248175B1

公开(公告)日：2001-06-19

申请号：US09430001

申请日：1999-10-29

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur

IPC分类号： B05C1100

CPC分类号： H01L21/6715 ,  G03F7/3021

摘要： A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position. A method of adjusting the offset position and/or volume of developer material applied at the first and second position is also provided. The method utilizes developed photoresist material layer thickness data provided by a measurement system to adjust the offset position and/or volume of the developer.

摘要翻译： 提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。 该系统包括适于沿着具有大致等于光致抗蚀剂材料层的直径的直线路径的光致抗蚀剂材料层上施加预定体积的显影剂材料的喷嘴。 移动系统将喷嘴移动到偏离光致抗蚀剂材料层的中心区域的第一位置，以在旋转涂覆显影剂材料的同时将第一预定体积的显影剂材料施加到光致抗蚀剂材料层。 移动系统还将喷嘴移动到偏离中心区域的第二位置，以在显影剂被旋涂时施加第二预定体积的显影剂材料到光致抗蚀剂材料层。 第一位置相对于第二位置位于中心区域的相反侧。 还提供了一种调节在第一和第二位置施加的显影剂材料的偏移位置和/或体积的方法。 该方法利用由测量系统提供的显影的光致抗蚀剂材料层厚度数据来调节显影剂的偏移位置和/或体积。

公开(公告)号：US5920786A

公开(公告)日：1999-07-06

申请号：US60894

申请日：1998-05-14

申请人： Tuan D. Pham ,  Michael K. Templeton

发明人： Tuan D. Pham ,  Michael K. Templeton

IPC分类号： G03F7/00 ,  G03F7/20 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L29/68 ,  G03C5/00 ,  G03F9/00

CPC分类号： H01L21/3086 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/3065 ,  H01L21/76232

摘要： The present invention provides a method of constructing trenches for use in microelectronic circuit structures. A photolithographic method is used to create trenches with sloped walls shaping the photoresist masks into sloped profiles. These photoresist masks effectively shape the underlying substrate during subsequent etch steps producing sloped wall trenches. These trenches can be used as shallow trench isolation structures to isolate microelectronic circuit structures from each other.

摘要翻译： 本发明提供一种构建用于微电子电路结构的沟槽的方法。 使用光刻方法来产生具有将光致抗蚀剂掩模成形为倾斜轮廓的倾斜壁的沟槽。 这些光致抗蚀剂掩模在随后的蚀刻步骤中有效地塑造下面的衬底，产生倾斜的壁沟槽。 这些沟槽可以用作浅沟槽隔离结构，以隔离微电子电路结构。