公开(公告)号：US12242374B2

公开(公告)日：2025-03-04

申请号：US17892535

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device. The processing device can provide, to a host system, usable capacity information and supported logical address granularity information for the logical address space. The processing device can obtain, from the host system, a logical address granularity configuration for a partition of the logical address space. The processing device can provide, to the host system, an acknowledgement of receipt of the logical address granularity configuration.

公开(公告)号：US12124721B2

公开(公告)日：2024-10-22

申请号：US17892607

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device, to perform operations including providing, to a host system, power safety capability information for the logical address space, obtaining, from the host system, a power safety configuration for a partition of the logical address space, and providing, to the host system, an acknowledgement of receipt of the power safety configuration.

公开(公告)号：US20240320153A1

公开(公告)日：2024-09-26

申请号：US18616993

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/0811 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0882 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0882 ,  G06F12/0891

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

公开(公告)号：US20240281374A1

公开(公告)日：2024-08-22

申请号：US18443005

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0646 ,  G06F12/0246 ,  G06F12/0292

Abstract: Methods, systems, and devices for address mapping table compression are described. A memory system may identify, for a region of an address mapping table, sets of sequentially indexed logical addresses that are mapped to sets of sequentially indexed physical addresses. The memory system may select a compression factor for the region based on the sets of sequentially indexed logical addresses. And the memory system may remove subsets of physical addresses from the sets of sequentially indexed physical addresses in the region based on the compression factor.

公开(公告)号：US20240184463A1

公开(公告)日：2024-06-06

申请号：US18511807

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for data type based write management techniques are described. A memory system may store (e.g., multiplex) different subsets of logical data types into the same data blocks and later separate the different types of logical data into respective data blocks. For example, the memory system may write each logical data type to a certain type of memory cell. The memory system may write different logical data types to the same type of memory cell and later separate them into the respective data blocks. For example, the memory system may write first data of a first logical data type and second data of a second logical data type to the same data block if both logical data types are associated with storage to the same type of memory cell and subsequently transfer the first data and second data to respective data blocks.

公开(公告)号：US11989456B2

公开(公告)日：2024-05-21

申请号：US17771668

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Xinghui Duan ,  Massimo Zucchinali

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7202

Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).

公开(公告)号：US11809311B2

公开(公告)日：2023-11-07

申请号：US17397393

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Christian M. Gyllenskog ,  Jonathan Scott Parry ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0629 ,  G06F12/0253 ,  G06F12/0292

Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.

公开(公告)号：US20230315569A1

公开(公告)日：2023-10-05

申请号：US18206398

申请日：2023-06-06

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F13/4221 ,  G06F12/1408 ,  G06F2212/7201

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US11721388B2

公开(公告)日：2023-08-08

申请号：US17708629

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C11/409 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

CPC classification number: G11C11/409 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1408 ,  G06F2212/7201

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a flash storage system. In an example, read commands or write commands can optionally include a file-type indicator. The file-type indicator can allow for exchange of data between the host and the flash storage system using a single record of a Flash Translation Layer (FTL) table or logical-to-physical (L2P) table, and where the amount of data can be much larger than the atomic unit associated with the flash storage system.

公开(公告)号：US11621042B2

公开(公告)日：2023-04-04

申请号：US17232725

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C16/26 ,  G11C16/32 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.