中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

78 records (took 0.025 seconds)

    3D NAND memory with built-in capacitor
    62.
    发明授权
    3D NAND memory with built-in capacitor 有权

    公开(公告)号：US12170117B2

    公开(公告)日：2024-12-17

    申请号：US17879356

    申请日：2022-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G11C16/30

    Abstract: An apparatus that includes a set of memory components of a memory sub-system is provided. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

    PADDING IN FLASH MEMORY BLOCKS
    63.
    发明申请
    PADDING IN FLASH MEMORY BLOCKS 有权

    公开(公告)号：US20240395329A1

    公开(公告)日：2024-11-28

    申请号：US18793392

    申请日：2024-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Murong Lang

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10

    Abstract: A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.

    LEVEL-BASED DATA REFRESH IN A MEMORY SUB-SYSTEM
    64.
    发明申请
    LEVEL-BASED DATA REFRESH IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20240386974A1

    公开(公告)日：2024-11-21

    申请号：US18662945

    申请日：2024-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C29/52

    Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including writing data to an MU of the memory device and performing one or more scan operations on the MU to determine an aggregate value of a data state metric reflective of an amount of erroneous memory cells in the MU. The operations can include determining whether a value of the data state metric reflective of a specified set of erroneous memory cells in the MU satisfies a criterion and identifying a target programming level to which at least one erroneous memory cell was originally programmed. They can also include reprogramming the at least one erroneous memory cell to the target programming level.

    MACHINE LEARNING-BASED ADJUSTMENT OF MEMORY CONFIGURATION PARAMETERS
    65.
    发明公开
    MACHINE LEARNING-BASED ADJUSTMENT OF MEMORY CONFIGURATION PARAMETERS 审中-公开

    公开(公告)号：US20240330717A1

    公开(公告)日：2024-10-03

    申请号：US18597851

    申请日：2024-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Wei Wang ,  Zhenming Zhou

    IPC: G06N5/022 ,  G06F12/02

    CPC classification number: G06N5/022 ,  G06F12/0246

    Abstract: A method for using and system for training a trainable model to predict values of memory configuration parameters based on a value of a performance metric. The value of the performance metric is based on a threshold condition of a memory access operation performed on a memory device using a set of values of the memory configuration parameters. The output of the trainable model includes a set of predicted values of the memory configuration parameters. Responsive to determining that the set of predicted values of the memory configuration parameters satisfies a confidence criterion, the memory configuration parameters are updated to reflect the set of predicted values of the memory configuration parameters.

    PARTIALLY GOOD BLOCK HANDLING IN A MEMORY DEVICE
    66.
    发明公开
    PARTIALLY GOOD BLOCK HANDLING IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240330094A1

    公开(公告)日：2024-10-03

    申请号：US18618639

    申请日：2024-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Jiangli Zhu ,  Zhenming Zhou

    IPC: G06F11/07

    CPC classification number: G06F11/0775 ,  G06F11/0727

    Abstract: A programming failure is detected at a block of a memory device. Based on detecting the programming failure, the block is determined to be partially good based on a number of failed bytes in the block. An unfailing portion of the block is identified in response to determining the block is partially good. A record indicating the block is partially good and identifying the unfailing portion of the block is stored.

    MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM
    69.
    发明公开
    MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240203507A1

    公开(公告)日：2024-06-20

    申请号：US18531100

    申请日：2023-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Tomer Tzvi Eliash ,  Yu-Chung Lien ,  Zhengang Chen ,  Jameer Mulani

    IPC: G11C16/10 ,  G11C16/08 ,  G11C29/52

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C29/52

    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first wordline of a first die of the memory device. The processing device identifies, based on a first predefined value, a second wordline of a second die of the memory device, wherein the first predefined value is a shift in an index value of the first wordline of the first die of the memory device. The processing device further performs a second programming operation on a second set of cells associated with the second wordline of the second die, wherein the second wordline of the second die is associated with a different index value than the first wordline of the first die.

    BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK
    70.
    发明公开
    BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK 审中-公开

    公开(公告)号：US20240185935A1

    公开(公告)日：2024-06-06

    申请号：US18524712

    申请日：2023-11-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.

Patent Agency Ranking