公开(公告)号：US06437407B1

公开(公告)日：2002-08-20

申请号：US09706807

申请日：2000-11-07

申请人： Ming-Dou Ker ,  Chyh-Yih Chang

发明人： Ming-Dou Ker ,  Chyh-Yih Chang

IPC分类号： H01L2362

CPC分类号： H01L27/0251

摘要： A charged-device model (CDM) electrostatic discharge (ESD) protection for complementary metal oxide semiconductor (CMOS) integrated circuits such as input/output (I/O) circuits. A CDM ESD clamp device is disposed on an output buffer or an input stage of the CMOS circuit in order to clamp the CDM ESD overstress voltage across the gate oxide during a CDM ESD event. When applied to I/O circuits, a bi-directional diode string with multiple diodes is used in conjunction with the CDM ESD clamp device. During the CDM ESD event, CDM charges (CDM Q) originally stored in the common substrate are discharged through the desired CDM ESD clamp device so as to protect all functional devices in the input, output or I/O circuits, and effectively improve the CDM ESD level in integrated circuit (IC) products.

摘要翻译： 用于互补金属氧化物半导体（CMOS）集成电路（例如输入/输出（I / O））电路的充电器件型号（CDM）静电放电（ESD）保护。 CDM ESD钳位器件设置在CMOS电路的输出缓冲器或输入级上，以便在CDM ESD事件期间钳位栅极氧化物上的CDM ESD过应力电压。 当应用于I / O电路时，具有多个二极管的双向二极管串与CDM ESD钳位装置结合使用。 在CDM ESD事件期间，原始存储在公共基板中的CDM充电（CDM Q）通过所需的CDM ESD钳位装置放电，以保护输入，输出或I / O电路中的所有功能器件，并有效改善CDM 集成电路（IC）产品中的ESD电平。

公开(公告)号：US06388850B1

公开(公告)日：2002-05-14

申请号：US09376066

申请日：1999-08-17

申请人： Ming-Dou Ker ,  Chen-Chia Wang ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Chen-Chia Wang ,  Hun-Hsien Chang

IPC分类号： H02H900

CPC分类号： H01L27/0251 ,  H02H9/046

摘要： An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), applied in an internal circuit and an input pad, both coupled with a first power line and a second power line, comprises a voltage clamp circuit and a voltage bias circuit. The voltage clamp circuit, with a transistor, connects to the second power line for clamping potential level through the voltage clamp circuit. The voltage bias circuit, with at least one diode coupled in series, connects to the voltage clamp circuit and the first power line for biasing the voltage clamp circuit to the second power line.

摘要翻译： 防止集成电路与施加在内部电路中的静电放电（ESD）干扰的装置和与第一电力线和第二电力线耦合的输入焊盘的装置包括电压钳位电路和电压偏置电路。 具有晶体管的电压钳位电路连接到第二电源线，用于通过电压钳位电路钳位电位电平。 具有串联耦合的至少一个二极管的电压偏置电路连接到电压钳位电路和用于将电压钳位电路偏压到第二电力线的第一电力线。

公开(公告)号：US6075686A

公开(公告)日：2000-06-13

申请号：US890660

申请日：1997-07-09

申请人： Ming-Dou Ker

发明人： Ming-Dou Ker

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： An ESD protected circuit is provided for protecting first and second internal circuits against ESD failure. The first and second internal circuits are respectively connected to either a first or a second power supply bus. The first and second power supply busses are mutually isolated from each other and are of the same polarity. The ESD protected circuit includes a first ESD protection circuit connected to the first power supply bus. A second ESD protection circuit is also provided which is connected to the second power supply bus. A third ESD protection circuit is connected between the first and second power supply busses. The third ESD protection circuit is for selectively connecting the first and second power supply busses only during an ESD event so that ESD energy applied to one of the first or second power supply busses couples to a second one of the first or second power supply busses. ESD energy coupled between the first and second power supply busses is also coupled through at least one of the first or second ESD protection circuits to ground.

摘要翻译： 提供ESD保护电路用于保护第一和第二内部电路免受ESD故障。 第一和第二内部电路分别连接到第一或第二电源总线。 第一和第二电源总线彼此相互隔离并具有相同的极性。 ESD保护电路包括连接到第一电源总线的第一ESD保护电路。 还提供了连接到第二电源总线的第二ESD保护电路。 第三个ESD保护电路连接在第一和第二电源总线之间。 第三ESD保护电路仅用于在ESD事件期间选择性地连接第一和第二电源总线，使得施加到第一或第二电源总线中的一个的ESD能量耦合到第一或第二电源总线中的第二电源总线。 耦合在第一和第二电源总线之间的ESD能量也通过第一或第二ESD保护电路中的至少一个耦合到地。

公开(公告)号：US6046087A

公开(公告)日：2000-04-04

申请号：US247792

申请日：1999-02-10

申请人： Geeng-Lih Lin ,  Ming-Dou Ker

发明人： Geeng-Lih Lin ,  Ming-Dou Ker

IPC分类号： H01L27/02 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L27/0266

摘要： In this invention a second gate is created in the area of the drain of a host transistor. The second gate overlies an N-well region and separates the drain of the host transistor into two portions. One portion of the drain is between the field oxide and the second gate and contains the contact for the drain. The second portion of the drain lies between the first gate which controls current in the drain and the second gate. The second gate provides a mask for the siliciding of the drain and provides a high impedance to drain current. In the event of an ESD, drain current is forced down into the N-well through one portion of the drain, under the second gate, and back up through the second portion of the drain providing a longer path and additional bulk material into which to dissipate the energy from an ESD event. Without using an extra mask to block the silicide, the second gate provides a silicide blocking effect to the drain of the ESD protection device.

摘要翻译： 在本发明中，在主晶体管的漏极区域中产生第二栅极。 第二栅极覆盖N阱区，并将主晶体管的漏极分成两部分。 漏极的一部分在场氧化物和第二栅极之间并且包含用于漏极的触点。 漏极的第二部分位于控制漏极中的电流的第一栅极和第二栅极之间。 第二个栅极为漏极的硅化物提供掩模，并提供高阻抗到漏极电流。 在ESD的情况下，漏极电流通过漏极的一部分被迫下降到N阱中，在第二栅极下方，并且通过漏极的第二部分向后延伸，提供更长的路径和额外的散装材料， 从ESD事件中消耗能量。 不使用额外的掩模来阻挡硅化物，第二栅极为ESD保护器件的漏极提供硅化物阻挡效应。

公开(公告)号：US5892262A

公开(公告)日：1999-04-06

申请号：US655073

申请日：1996-06-03

申请人： Chau-Neng Wu ,  Ming-Dou Ker

发明人： Chau-Neng Wu ,  Ming-Dou Ker

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： A capacitor-triggered electrostatic discharge (ESD) protection circuit is disposed between a metal pad and V.sub.ss potential level, wherein the pad may be an input pad, an output pad, or a V.sub.DD power rail. The circuit includes a thick oxide device, a capacitor, and a resistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground V.sub.SS, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is coupled by the resistor to circuit ground V.sub.SS. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout areas. When a positive-to-ground ESD pulse is conducted at the pad, the capacitor will couple the ESD voltage to the well region, forward bias the bulk/source junction, and then turn on the thick oxide device operated in a bipolar mode to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra or built-in PN junction.

摘要翻译： 电容触发的静电放电（ESD）保护电路设置在金属焊盘和Vss电位之间，其中焊盘可以是输入焊盘，输出焊盘或VDD电源轨。 该电路包括厚氧化物，电容器和电阻。 厚氧化物器件被配置为其漏极和源极分别连接到焊盘和电路接地VSS。 厚氧化物器件的栅极连接到焊盘，并且氧化物器件体积被电阻器耦合到电路接地VSS。 电容器连接在焊盘和厚氧化物器件的主体之间。 器件的主体由形成在衬底中的P阱区域构成。 电容器形成在焊盘和刚好在其之间的多晶硅层之间，而不消耗额外的布局面积。 当在焊盘上进行正对地ESD脉冲时，电容器将ESD静电电压耦合到阱区域，正向偏置体/源极结，然后打开以双极模式工作的厚氧化物器件旁路 ESD应力。 此外，二极管分别通过其阴极和阳极连接在焊盘和电路接地之间，以绕过负对地ESD脉冲。 二极管可以是额外的或内置的PN结。

公开(公告)号：US5744842A

公开(公告)日：1998-04-28

申请号：US698241

申请日：1996-08-15

申请人： Ming-Dou Ker

发明人： Ming-Dou Ker

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： An electrostatic discharge (ESD) protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, and which includes an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit driven by the transient detection circuit and connected between the VDD and VSS lines, wherein the discharge circuit includes a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein the bipolar transistor is implemented by a structure selected from a group consisting of a vertical bipolar transistor and a field oxide device, and wherein the bipolar transistor has a base that is driven by the transient detection circuit.

摘要翻译： 一种静电放电（ESD）保护电路，其形成具有VDD线和VSS线的集成电路的一部分，并且包括连接在VDD和VSS线之间的ESD瞬态检测电路; 以及由瞬态检测电路驱动并连接在VDD和VSS线之间的静电放电电路，其中放电电路包括具有发射极和集电极的双极晶体管，其中一个电极与VDD线电连接，另一个 电连接到VSS线，其中所述双极晶体管由选自由垂直双极晶体管和场氧化物器件组成的组中的结构实现，并且其中所述双极晶体管具有由所述瞬态检测电路驱动的基极。

公开(公告)号：US5721656A

公开(公告)日：1998-02-24

申请号：US661105

申请日：1996-06-10

申请人： Chau-Neng Wu ,  Ming-Dou Ker

发明人： Chau-Neng Wu ,  Ming-Dou Ker

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0251

摘要： An electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.

摘要翻译： 一种静电放电保护网络，其转移IC器件的任何两个接触焊盘之间产生的ESD应力，以防止损坏IC器件的内部电路。 ESD放电总线设置在IC芯片的周围。 在每个IC焊盘和放电总线之间，有一个保护电路直接绕过任何两个IC焊盘产生的ESD应力。 每个ESD保护电路包括二极管，厚氧化物装置，电阻器和电容器。 保护电路以快速恢复模式运行，不会导致故障。 因此，ESD保护电路的触发电压降低到回跳电压的水平，但不降低到击穿电压的水平。

公开(公告)号：US08829775B2

公开(公告)日：2014-09-09

申请号：US13464506

申请日：2012-05-04

申请人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

发明人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

IPC分类号： H01J1/88 ,  H01J19/42 ,  H01J1/00 ,  H01J1/18

CPC分类号： H01J9/02 ,  H01J17/066

摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.

摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。

公开(公告)号：US20130221834A1

公开(公告)日：2013-08-29

申请号：US13464506

申请日：2012-05-04

申请人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

发明人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

IPC分类号： H01J1/88 ,  C23C16/44 ,  B05D5/12

CPC分类号： H01J9/02 ,  H01J17/066

摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.

摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。

公开(公告)号：US08498085B2

公开(公告)日：2013-07-30

申请号：US13589285

申请日：2012-08-20

申请人： Federico A. Altolaguirre ,  Ming-Dou Ker ,  Chua-Chin Wang

发明人： Federico A. Altolaguirre ,  Ming-Dou Ker ,  Chua-Chin Wang

IPC分类号： H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

CPC分类号： H02H9/046

摘要： An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.

摘要翻译： 具有泄漏电流降低功能的ESD保护电路包括可控硅整流器，第一CMOS反相器，第一晶体管，电流镜，PMOS电容器和电阻器。 第一个CMOS反相器与可控硅整流器电连接。 第一晶体管包括第一端，第二端和第三端，其中第一端与可控硅整流器和第一CMOS反相器电连接，并且电流镜与第一晶体管的第三端电连接。 PMOS电容器与电流镜电连接，并且电阻器与第一CMOS反相器，第一晶体管的第二端和PMOS电容器电连接。