公开(公告)号：US09467378B1

公开(公告)日：2016-10-11

申请号：US14634849

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A method involving a Software-Defined Networking (SDN) switch. A packet is received onto a SDN switch via a NFX circuit. The NFX circuit determines that the packet matches no flow entry stored in any flow table in the NFX circuit and forwards the packet to a NFP circuit. The NFP circuit determines that the packet matches a first flow entry that applies to a relatively broad flow of packets stored in a flow table in the NFP circuit, generates a new flow entry that applies to a relatively narrow subflow of packets, and forwards the new flow entry to the NFX circuit that stores the new flow entry in a flow table in the NFX circuit. A subsequent packet is received onto the SDN switch via the NFX circuit and is switched using the new flow entry stored in the NFX circuit without forwarding the packet to the NFP circuit.

Abstract translation: 一种涉及软件定义网络（SDN）交换机的方法。 通过NFX电路将数据包接收到SDN交换机上。 NFX电路确定该分组与NFX电路中任何流表中存储的流条目匹配，并将数据包转发到NFP电路。 NFP电路确定该分组与适用于存储在NFP电路中的流表中的相对广泛的分组流的第一流条目匹配，生成适用于相对窄的分组子流的新流入口，并转发新的 流入NFX电路，将新流入口存储在NFX电路的流表中。 随后的数据包经由NFX电路接收到SDN交换机上，并使用存储在NFX电路中的新流程进行切换，而不将数据包转发到NFP电路。

公开(公告)号：US09450890B2

公开(公告)日：2016-09-20

申请号：US13941484

申请日：2013-07-13

Applicant: Netronome Systems, Inc.

Inventor： Chirag P. Patel ,  Gavin J. Stark

IPC: H04L12/931

CPC classification number: H04L49/20

Abstract: An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.

Abstract translation: 出口分组修饰符包括脚本解析器和处理阶段的流水线。 而不是使用处理器执行出口修改，处理器以经典处理器的方式获取和解码并执行指令，而不是将数据包存储在存储器中并将其读出并修改它并将其写回来，数据包修改器流水线通过传递来处理数据包 部分数据包通过管道。 处理器通过将脚本代码放置在分组的开始处来识别要执行的特定出口修改。 脚本解析器然后使用代码来识别操作码的特定脚本，其中每个操作码定义了一个修改。 作为一个阶段，舞台可以进行这样一个操作码的修改。 通过使用当前的半导体制造工艺实现，分组修改器可以以高达100吉比特/秒的持续速率修改200M分组/秒。

公开(公告)号：US09417844B2

公开(公告)日：2016-08-16

申请号：US14037312

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F7/58

CPC classification number: G06F7/584

Abstract: A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers.

Abstract translation: 自定时逻辑熵比特流发生器（STLEBSG）输出具有非确定性熵的比特流。 比特流被提供到信号存储环的输入端，使得当比特流在环中循环时，比特流的熵随后被存储在环中。 根据环的配置，其循环中的位流经历置换，但是信号存储环仍然存储注入的比特流的熵。 在一个示例中，STLEBSG被禁用并且比特流不再被提供给环，但是环继续循环并存储原始比特流的熵。 禁用STLEBSG时，使用来自环的信号输出来产生一个或多个随机数。

公开(公告)号：US09401880B1

公开(公告)日：2016-07-26

申请号：US14588084

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

IPC: H04L12/54 ,  G06F15/80 ,  H04L12/861 ,  H04L12/933 ,  H04L12/801

CPC classification number: H04L49/9047 ,  H04L47/13 ,  H04L49/102 ,  H04L49/9084

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

公开(公告)号：US09389908B1

公开(公告)日：2016-07-12

申请号：US14588280

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/02

CPC classification number: G06F9/467 ,  G06F9/34 ,  G06F12/023 ,  G06F12/08 ,  G06F2212/251

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.

公开(公告)号：US09282051B2

公开(公告)日：2016-03-08

申请号：US13928235

申请日：2013-06-26

Applicant: Netronome Systems, Inc.

Inventor： Richard P. Bouley ,  Gavin J. Stark

IPC: G06F9/46 ,  H04L12/801 ,  H04L12/911

CPC classification number: H04L47/39 ,  H04L47/822

Abstract: A high-speed credit-based allocator circuit receives an allocation request to make an allocation to one of a set of a processing entities. The allocator circuit maintains a chain of bubble sorting module circuits for the set, where each bubble sorting module circuit stores a resource value and an indication of a corresponding processing entity. A bubble sorting operation is performed so that the head of the chain tends to indicate the processing entity of the set that has the highest amount of the resource (credit) available. The allocation requested is made to the processing entity indicated by the head module circuit of the chain. The amount of the resource available to each processing entity is tracked by adjusting the resource values as allocations are made, and as allocated tasks are completed. The allocator circuit is configurable to maintain multiple chains, thereby supporting credit-based allocations to multiple sets of processing entities.

Abstract translation: 高速信用分配器电路接收分配请求以对一组处理实体之一进行分配。 分配器电路为该组保持一连串的气泡分类模块电路，其中每个气泡分选模块电路存储资源值和对应的处理实体的指示。 执行气泡排序操作，使得链的头倾向于指示具有最高资源量（信用）可用的集合的处理实体。 所请求的分配是由链的头模块电路指示的处理实体。 每个处理实体可用的资源量通过调整资源值进行跟踪，当分配完成时，并且分配的任务完成。 分配器电路可配置为维护多个链，从而支持基于信用的分配给多组处理实体。

公开(公告)号：US20150317162A1

公开(公告)日：2015-11-05

申请号：US14267329

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/32 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/448

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Abstract translation: 流水线运行完成处理器不包括指令计数器，并且仅获取指令：由于通过输入数据值和/或初始提取信息值从外部提示，或作为执行执行的结果 指令。 最初处理器没有计时。 输入值启动，启动处理器开始计时，并从表中的代码段获取指令块。 输入数据值和/或初始获取信息值确定从其获取块的部分和表。 LUT将初始获取信息值中的表号转换为找到表的基地址。 在代码段的末尾获取指令导致程序执行从一个部分跳转到另一个部分。 完成的指令将输出一个输出数据值，并停止处理器的时钟。

公开(公告)号：US20150293578A1

公开(公告)日：2015-10-15

申请号：US14251599

申请日：2014-04-12

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F1/32

CPC classification number: G06F15/80 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/4843 ,  G06F9/5027 ,  G06F9/5038 ,  G06F15/8007 ,  G06F15/8046 ,  G06F15/8053 ,  Y02D10/171 ,  Y02D10/24

Abstract: A general purpose PicoEngine Multi-Processor (PEMP) includes a hierarchically organized pool of small specialized picoengine processors and associated memories. A stream of data input values is received onto the PEMP. Each input data value is characterized, and from the characterization a task is determined. Picoengines are selected in a sequence. When the next picoengine in the sequence is available, it is then given the input data value along with an associated task assignment. The picoengine then performs the task. An output picoengine selector selects picoengines in the same sequence. If the next picoengine indicates that it has completed its assigned task, then the output value from the selected picoengine is output from the PEMP. By changing the sequence used, more or less of the processing power and memory resources of the pool is brought to bear on the incoming data stream. The PEMP automatically disables unused picoengines and memories.

Abstract translation: 通用PicoEngine多处理器（PEMP）包括一个分层组织的小型专用微型引擎处理器和相关存储器的池。 数据输入值流被接收到PEMP上。 每个输入数据值被表征，并且从表征确定任务。 Picoengines按顺序选择。 当序列中的下一个微型引擎可用时，然后给出输入数据值以及相关的任务分配。 picoengine然后执行任务。 输出微型引擎选择器以相同的顺序选择微型引线。 如果下一个微微引擎指示它已经完成其分配的任务，则从PEMP输出所选择的微微引擎的输出值。 通过改变所使用的顺序，或多或少地将该池的处理能力和存储器资源承担在输入数据流上。 PEMP自动禁用未使用的打印机和内存。

公开(公告)号：US20150220445A1

公开(公告)日：2015-08-06

申请号：US14172856

申请日：2014-02-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F12/10 ,  G06F9/46

CPC classification number: G06F9/467 ,  G06F12/109 ,  G06F13/385 ,  G06F2212/151 ,  G06F2212/657 ,  G06F2213/0026

Abstract: A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the transactional memory is enabled to do address translations and if the command is for an access (read or write) of a memory of the transactional memory, then the transactional memory performs an address translation operation on the address of the command. Parameters of the address translation are programmable and are set up before the command is received. In one configuration, certain bits of the incoming address are deleted, and other bits are shifted in bit position, and a base address is ORed in, and a padding bit is added, thereby generating the translated address. The resulting translated address is then used to access the memory of the transactional memory to carry out the command.

Abstract translation: 事务存储器接收命令，其中命令包括地址和小写的DAT（地址转换）位。 如果DAT位被设置，并且事务存储器被使能以进行地址转换，并且如果该命令用于访问（读或写）事务存储器的存储器，则事务存储器对该地址执行地址转换操作 的命令。 地址转换的参数是可编程的，并在接收到命令之前设置。 在一种配置中，输入地址的某些比特被删除，并且其他比特在比特位置被移位，并且基地址被加入，并且添加一个填充比特，从而生成翻译的地址。 然后，所得到的转换地址用于访问事务存储器的存储器以执行命令。

公开(公告)号：US20150193484A1

公开(公告)日：2015-07-09

申请号：US14151666

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F17/30

CPC classification number: H04L12/6418 ,  G06F9/4498 ,  G06F17/30283 ,  G11C15/00

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。