公开(公告)号：US20120112296A1

公开(公告)日：2012-05-10

申请号：US12943391

申请日：2010-11-10

申请人： Peter Smeys ,  Andrei Papou ,  Peter J. Hopper

发明人： Peter Smeys ,  Andrei Papou ,  Peter J. Hopper

IPC分类号： H01L29/82 ,  H01L21/02

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

摘要： The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.

摘要翻译： 电感器的电感通过形成导线而增加，其具有蛇形形状，该蛇形形状通过铁磁芯编织，所述铁磁芯具有以蛇形形式连接在一起的多个段，其中铁磁芯的每个段也具有多个部分 它们以蛇形形状连接在一起。

公开(公告)号：US20120002377A1

公开(公告)日：2012-01-05

申请号：US12827316

申请日：2010-06-30

申请人： William French ,  Peter J. Hopper ,  Peter Smeys ,  Ann Gabrys ,  David I. Anderson

发明人： William French ,  Peter J. Hopper ,  Peter Smeys ,  Ann Gabrys ,  David I. Anderson

IPC分类号： H05K7/02 ,  H05K3/36

CPC分类号： H01L23/645 ,  H01F2019/085 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19105 ,  H01L2924/3011 ,  Y10T29/49128 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween.

摘要翻译： 集成电路管芯系统包括第一集成电路管芯，第二集成电路管芯和形成在电介质（例如，石英））衬底上并电连接在第一集成电路管芯和第二集成电路管芯之间以提供电流隔离的变压器 。

公开(公告)号：US20090091414A1

公开(公告)日：2009-04-09

申请号：US11973536

申请日：2007-10-09

申请人： Peter J. Hopper ,  Peter Smeys ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Smeys ,  Andrei Papou

IPC分类号： H01F27/34 ,  H01F27/24 ,  H01F41/02

CPC分类号： H01F17/0013 ,  H01F3/14 ,  H01F27/34 ,  H01F41/046 ,  H01F2017/0066 ,  Y10T29/49078

摘要： Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.

摘要翻译： 用于大电流应用的片上电感器的非线性铁磁芯材料的饱和度通过提供其中磁通量不形成闭环但是分成多个子通量的核心设计而显着降低，这些子通量被引导以相互抵消。 该设计可实现高电流功率应用的高片上电感。

公开(公告)号：US06825097B2

公开(公告)日：2004-11-30

申请号：US10214510

申请日：2002-08-07

申请人： Klaus D. Beyer ,  Patricia A. O'Neil ,  Deborah A. Ryan ,  Peter Smeys ,  Effendi Leobandung

发明人： Klaus D. Beyer ,  Patricia A. O'Neil ,  Deborah A. Ryan ,  Peter Smeys ,  Effendi Leobandung

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

摘要翻译： 在包括沟槽器件隔离的SOI的集成电路工艺中，通过三重填充工艺来解决沟槽填充中的空隙的问题，其中在底部拐角处具有凹陷的热氧化物侧壁被LPCVD沉积覆盖，所述LPCVD沉积填充 凹陷，随后是无空隙的HDP沉积。 致密化导致三种类型氧化物基本上相同的蚀刻速率。

公开(公告)号：US06531365B2

公开(公告)日：2003-03-11

申请号：US09888160

申请日：2001-06-22

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Peter Smeys ,  Isabel Y. Yang

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Peter Smeys ,  Isabel Y. Yang

IPC分类号： H01L21336

CPC分类号： H01L21/82345

摘要： A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a first planarizing organic film on the gate dielectric material and abutting vertical sidewalls of the patterned gate stacks, said planarizing organic film not being present on top, horizontal surfaces of each of the patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and first planarizing organic film and forming a second planarizing organic film and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by said second resist; and removing the second resist and the second planarizing organic film.

摘要翻译： 提供了一种用于改善金属氧化物半导体场效应晶体管（MOSFET）结构的栅激活的方法。 本发明的方法包括以下步骤：在栅极电介质材料层的上方形成多个图案化的栅叠层; 在所述栅极电介质材料上形成第一平面化有机膜并邻接所述图案化栅极叠层的垂直侧壁，所述平面化有机膜不存在于每个所述图案化栅极堆叠的顶部水平表面上; 用第一抗蚀剂阻挡多个图案化栅极堆叠中的一些，同时留下所述多个未封装的其它图案化栅极堆叠; 将第一离子注入未封闭的图案化栅极堆叠中; 去除第一抗蚀剂和第一平面化有机膜并形成第二平面化有机膜并用第二抗蚀剂阻挡先前未封闭的图案化栅叠层; 将第二离子注入未被所述第二抗蚀剂阻挡的图案化栅极堆叠中; 并除去第二抗蚀剂和第二平面化有机膜。

公开(公告)号：US06323535B1

公开(公告)日：2001-11-27

申请号：US09595764

申请日：2000-06-16

申请人： Sundar K. Iyer ,  Peter Smeys ,  Chandrasekhar Narayan ,  Subramanian Iyer ,  Axel Brintzinger

发明人： Sundar K. Iyer ,  Peter Smeys ,  Chandrasekhar Narayan ,  Subramanian Iyer ,  Axel Brintzinger

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

摘要翻译： 根据本发明的用于半导体器件的熔丝包括第一掺杂剂类型的第一掺杂剂类型的阴极和包括第二掺杂剂类型的第二掺杂剂类型的阳极。 熔丝连接器连接阴极和阳极并且包括第二掺杂剂类型。 熔丝链和阴极在它们之间形成一个结，并且该结被配置为相对于阴极电位和阳极电位被反向偏置。 导电层跨越结形成，使得在结处流动的电流被转移到导电层中以增强材料迁移以对熔丝进行编程。