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公开(公告)号：US06825097B2
公开(公告)日：2004-11-30
申请号：US10214510
申请日：2002-08-07
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76283
摘要： In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.
摘要翻译： 在包括沟槽器件隔离的SOI的集成电路工艺中，通过三重填充工艺来解决沟槽填充中的空隙的问题，其中在底部拐角处具有凹陷的热氧化物侧壁被LPCVD沉积覆盖，所述LPCVD沉积填充 凹陷，随后是无空隙的HDP沉积。 致密化导致三种类型氧化物基本上相同的蚀刻速率。
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2.发明授权公开(公告)号：US07797652B2
公开(公告)日：2010-09-14
申请号：US12174924
申请日：2008-07-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.
摘要翻译： 实现集成电路产量估计的方法包括：计算用于原始集成电路布局的Voronoi区域; 对于Voronoi区域的每个平分线段和一个或多个故障机制，基于与等分线段相关联的相应Voronoi边缘区域的几何参数计算故障概率，使用预先计算的故障概率作为边缘取向和间距的函数 失效机制; 对于由平分线限定的设计边缘的每个段，使用预先计算的故障机制的故障概率的变化来计算基于Voronoi区域的几何参数的故障概率的变化; 以适合于用户的视觉差异的方式对每个Voronoi区域计算的故障概率进行编码; 并且通过将导致故障概率降低的布局边缘段的定向位移来编码所计算的故障概率的变化。
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公开(公告)号：US07189644B2
公开(公告)日：2007-03-13
申请号：US10763308
申请日：2004-01-23
IPC分类号： H01L21/4763 , H01L29/76
CPC分类号： H01L29/66507 , H01L29/665 , H01L29/6656
摘要： The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is produced by forming first suicide regions in a substrate as well as atop surface of a gate region and forming second silicide regions where second silicide thickness is greater than the first silicide thickness. The inventive method produces a low resistance first silicide in close proximity to the channel region of the device, where the incorporation of the first silicide decreases the external resistance of the device while the incorporation of the second silicide produces low sheet resistance interconnects.
摘要翻译： 本发明涉及具有较低外部电阻的互补金属氧化物半导体（CMOS）器件及其制造方法。 本发明的MOSFET通过在衬底以及栅极区域的顶表面上形成第一硅化物区域并形成其中第二硅化物厚度大于第一硅化物厚度的第二硅化物区域来制造。 本发明的方法在器件的沟道区域附近产生低电阻的第一硅化物，其中掺入第一硅化物降低了器件的外部电阻，同时掺入第二硅化物产生低的薄层电阻互连。
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4.发明授权Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design 有权集成电路设计中制造效果快速仿真的装置，方法和计算机程序产品公开(公告)号：US08117568B2
公开(公告)日：2012-02-14
申请号：US12237727
申请日：2008-09-25
申请人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
发明人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
CPC分类号： G06F17/5009 , G06F2217/12 , Y02P90/265
摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。
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5.发明申请Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design 有权集成电路设计中快速刺激制造效果的装置，方法和计算机程序产品公开(公告)号：US20100077372A1
公开(公告)日：2010-03-25
申请号：US12237727
申请日：2008-09-25
申请人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
发明人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/12 , Y02P90/265
摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。
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6.发明申请IMPLEMENTING INTEGRATED CIRCUIT YIELD ESTIMATION USING VORONOI DIAGRAMS 有权使用VORONOI DIAGRAMS实现集成电路的线性估计公开(公告)号：US20100017762A1
公开(公告)日：2010-01-21
申请号：US12174924
申请日：2008-07-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.
摘要翻译： 实现集成电路产量估计的方法包括：计算用于原始集成电路布局的Voronoi区域; 对于Voronoi区域的每个平分线段和一个或多个故障机制，基于与等分线段相关联的相应Voronoi边缘区域的几何参数计算故障概率，使用预先计算的故障概率作为边缘取向和间距的函数 失效机制; 对于由平分线限定的设计边缘的每个段，使用预先计算的故障机制的故障概率的变化来计算基于Voronoi区域的几何参数的故障概率的变化; 以适合于用户的视觉差异的方式对每个Voronoi区域计算的故障概率进行编码; 并且通过将导致故障概率降低的布局边缘段的定向位移来编码所计算的故障概率的变化。
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7.发明授权Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer 有权使用COR保护TEOS硬掩模，用于升高的源极漏极，包括可移动/一次性间隔件公开(公告)号：US06790733B1
公开(公告)日：2004-09-14
申请号：US10249296
申请日：2003-03-28
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/823814 , H01L21/823864 , H01L29/6653 , Y10S438/976
摘要： The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.
摘要翻译： 本发明提供了一种保护氧化物硬掩模的方法，其目的是避免在升高的源极/漏极形成期间栅极叠层上的外延Si的生长。 通过利用包括化学氧化物去除处理步骤而不是水性HF蚀刻剂的方法在本发明中保存氧化物硬掩模。
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