公开(公告)号：US07206903B1

公开(公告)日：2007-04-17

申请号：US10895519

申请日：2004-07-20

Applicant: Mark S. Moir ,  Maurice P. Herlihy ,  Quinn A. Jacobson ,  Shailender Chaudhry ,  Marc Tremblay

Inventor： Mark S. Moir ,  Maurice P. Herlihy ,  Quinn A. Jacobson ,  Shailender Chaudhry ,  Marc Tremblay

IPC: G06F12/00

CPC classification number: G06F12/0842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859

Abstract: One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.

Abstract translation: 本发明的一个实施例提供了一种用于将存储器位置从事务程序执行释放的系统。 该系统通过在事务性程序执行期间执行指令序列来操作，其中监视涉及事务性程序执行的存储器位置以检测来自其他线程的干扰访问，并且其中在事务执行期间进行的改变不会被提交直到事务执行完成而不遇到 干扰来自另一个线程的数据访问。 在事务性程序执行期间遇到存储器位置的释放指令时，系统修改处理器内的状态信息以从监视释放存储器位置。 该系统还执行commit-and-start-new-transaction指令，其中commit-and-start-new-transaction指令以原子方式提交事务的存储，从而在事务的读取集保持不受影响的情况下将其从事务的写入集中移除。

公开(公告)号：US07124331B2

公开(公告)日：2006-10-17

申请号：US10146102

申请日：2002-05-14

Applicant: Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

Inventor： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

IPC: G06F11/00

CPC classification number: G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

Abstract: One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

Abstract translation: 本发明的一个实施例提供一种在中央处理单元（CPU）内校正临时结果中的位错误的系统。 在运行期间，系统在执行飞行中指令时收到临时结果。 接下来，系统生成用于临时结果的奇偶校验位，并将临时结果和奇偶校验位存储在CPU内的临时寄存器中。 在临时结果提交到CPU的架构状态之前，系统会检查临时结果和奇偶校验位以检测位错误。 如果检测到位错误，则系统执行微陷阱操作以重新执行产生临时结果的指令，从而重新产生临时结果。 否则，如果未检测到位错误，则系统将临时结果提交给CPU的体系结构状态。

公开(公告)号：US07089374B2

公开(公告)日：2006-08-08

申请号：US10764412

申请日：2004-01-23

Applicant: Marc Tremblay ,  Quinn A. Jacobson ,  Shailender Chaudhry ,  Mark S. Moir ,  Maurice P. Herlihy

Inventor： Marc Tremblay ,  Quinn A. Jacobson ,  Shailender Chaudhry ,  Mark S. Moir ,  Maurice P. Herlihy

IPC: G06F12/00

CPC classification number: G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F12/0862

Abstract: One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.

Abstract translation: 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。

公开(公告)号：US06938130B2

公开(公告)日：2005-08-30

申请号：US10737679

申请日：2003-12-15

Applicant: Quinn A. Jacobson ,  Marc Tremblay ,  Shailender Chaudhry

Inventor： Quinn A. Jacobson ,  Marc Tremblay ,  Shailender Chaudhry

IPC: G06F9/46 ,  G06F12/08 ,  G06F9/38

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

公开(公告)号：US06247121B1

公开(公告)日：2001-06-12

申请号：US09157791

申请日：1998-09-21

Applicant: Haitham Akkary ,  Quinn A. Jacobson

Inventor： Haitham Akkary ,  Quinn A. Jacobson

IPC: C06F1500

CPC classification number: G06F9/3842 ,  G06F9/3013 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.

Abstract translation: 在一个实施例中，处理器包括线程管理逻辑，其包括具有状态机的线程预测器，以指示是否采取线程创建机会。 该处理器包括一个预测器训练机制，用于接收退休指令，并从退休指令中识别潜在的线程，并确定一个可能的线程是否满足线程精度的测试，并且如果该测试得到满足，那么状态机 与感兴趣的潜在线程相关联的更新在取向方向上，并且如果不满足测试，则状态机以不采取方向更新。 线程管理逻辑可以控制实际线程的创建，并且还可以包括复位逻辑以控制实际线程是否被重置，并且其中如果实际线程被重置，则与实际线程相关联的状态机之一被更新为不采用 方向。 最终退休逻辑可以控制实际线程是否退休，并且其中如果实际线程已经退休，则与实际线程相关联的状态机在取向方向上被更新。 电路可以与多线程处理器结合使用，该多线程处理器检测涉及执行实际线程中的线程相关性的推测误差，并重新执行与执行流水线之外的跟踪缓冲器的推测错误相关联的指令。