-
1.发明授权Selectively unmarking load-marked cache lines during transactional program execution 有权在事务性程序执行期间选择性地取消标记加载标记的高速缓存行公开(公告)号：US07389383B2
公开(公告)日：2008-06-17
申请号：US11399049
申请日：2006-04-06
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。
-
2.发明授权Method and apparatus for releasing memory locations during transactional execution 有权在事务执行期间释放内存位置的方法和装置公开(公告)号：US07206903B1
公开(公告)日：2007-04-17
申请号：US10895519
申请日：2004-07-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.
摘要翻译： 本发明的一个实施例提供了一种用于将存储器位置从事务程序执行释放的系统。 该系统通过在事务性程序执行期间执行指令序列来操作，其中监视涉及事务性程序执行的存储器位置以检测来自其他线程的干扰访问，并且其中在事务执行期间进行的改变不会被提交直到事务执行完成而不遇到 干扰来自另一个线程的数据访问。 在事务性程序执行期间遇到存储器位置的释放指令时，系统修改处理器内的状态信息以从监视释放存储器位置。 该系统还执行commit-and-start-new-transaction指令，其中commit-and-start-new-transaction指令以原子方式提交事务的存储，从而在事务的读取集保持不受影响的情况下将其从事务的写入集中移除。
-
3.发明授权Selectively unmarking load-marked cache lines during transactional program execution 有权在事务性程序执行期间选择性地取消标记加载标记的高速缓存行公开(公告)号：US07089374B2
公开(公告)日：2006-08-08
申请号：US10764412
申请日：2004-01-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。
-
4.发明授权Logical power throttling of instruction decode rate for successive time periods 有权连续时间段的逻辑功率节制指令解码速率公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
-
5.发明授权Start transactional execution (STE) instruction to support transactional program execution 有权启动事务执行（STE）指令以支持事务性程序执行公开(公告)号：US07500086B2
公开(公告)日：2009-03-03
申请号：US11296599
申请日：2005-12-06
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译： 本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。 在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。 在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。
-
公开(公告)号：US07418577B2
公开(公告)日：2008-08-26
申请号：US10637169
申请日：2003-08-08
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
摘要翻译： 本发明的一个实施例提供一种支持执行失败指令的系统，其终止指令块的事务执行。 在操作期间，系统促进程序内的指令块的事务执行，其中在事务执行期间所做的更改不会被提交到处理器的体系结构状态，直到事务执行成功完成。 如果在此事务执行期间遇到失败指令，则系统终止事务执行，而不将事务执行的结果提交给处理器的体系结构状态。
-
公开(公告)号：US20070226467A1
公开(公告)日：2007-09-27
申请号：US11425869
申请日：2006-06-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译： 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。
-
公开(公告)号：US20100191993A1
公开(公告)日：2010-07-29
申请号：US12361422
申请日：2009-01-28
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
-
公开(公告)号：US07565511B2
公开(公告)日：2009-07-21
申请号：US11425869
申请日：2006-06-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译： 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。
-
公开(公告)号：US07509481B2
公开(公告)日：2009-03-24
申请号：US11277735
申请日：2006-03-28
IPC分类号： G06F9/00
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。 例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。 可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。 类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。 在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。 在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。
-
-
-
-
-
-
-
-
-
搜索结果
240 条记录 (耗时 0.032 秒)
