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公开(公告)号：US11683206B2
公开(公告)日：2023-06-20
申请号：US17323271
申请日：2021-05-18
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
CPC classification number: H04L25/4917 , H04L7/0058 , H04L7/0331 , H04L25/03057
Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US11683057B2
公开(公告)日：2023-06-20
申请号：US17527631
申请日：2021-11-16
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
CPC classification number: H04B1/123 , H04B1/12 , H04L25/0264 , H04L25/03057 , H04L25/03076 , H04L25/03133 , H04L25/4917 , H04L27/00 , H04L27/01 , H04L27/06
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US11575386B2
公开(公告)日：2023-02-07
申请号：US17315699
申请日：2021-05-10
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US11411787B2
公开(公告)日：2022-08-09
申请号：US17363557
申请日：2021-06-30
Applicant: Rambus Inc.
Inventor： Masum Hossain , Richelle L. Smith , Carl W. Werner
IPC: H04L27/227 , H04L27/233 , H04L27/34 , H04L27/20
Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.
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公开(公告)号：US20220103404A1
公开(公告)日：2022-03-31
申请号：US17400823
申请日：2021-08-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Maruf H. Mohammad
Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.
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Patent Agency Ranking
公开(公告)号：US20210344529A1
公开(公告)日：2021-11-04
申请号：US17323271
申请日：2021-05-18
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US11088880B2
公开(公告)日：2021-08-10
申请号：US16864079
申请日：2020-04-30
Applicant: Rambus Inc.
Inventor： Masum Hossain , Richelle L. Smith , Carl W. Werner
IPC: H04L27/20 , H04L27/233 , H04L27/34
Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.
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公开(公告)号：US20200313938A1
公开(公告)日：2020-10-01
申请号：US16847793
申请日：2020-04-14
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US10707885B2
公开(公告)日：2020-07-07
申请号：US16272236
申请日：2019-02-11
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US10608652B2
公开(公告)日：2020-03-31
申请号：US16247894
申请日：2019-01-15
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
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