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公开(公告)号：US07962696B2
公开(公告)日：2011-06-14
申请号：US10758368
申请日：2004-01-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of owner predictors in response to a change in an ownership state of the block of data. The update message comprises an address tag associated with the block of data and an identification associated with an owner node of the block of data.
摘要翻译： 公开了用于更新所有者预测器结构的系统和方法。 在一个实施例中，多处理器系统包括所有者预测器控制，其响应于所述数据块的所有权状态的改变，将对应于数据块的所有权更新消息提供给多个所有者预测器中的至少一个 。 更新消息包括与数据块相关联的地址标签和与该数据块的所有者节点相关联的标识。
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公开(公告)号：US07818391B2
公开(公告)日：2010-10-19
申请号：US10761048
申请日：2004-01-20
IPC分类号： G06F15/16
CPC分类号： G06F12/0833 , G06F12/0817
摘要： A system includes a first node that broadcasts a request for data. A second node having a first state associated with the data defines the second node as an ordering point for the data. The second node provides a response to the first node that transfers the ordering point to the first node in response to the request for the data.
摘要翻译： 系统包括广播数据请求的第一节点。 具有与数据相关联的第一状态的第二节点将第二节点定义为数据的排序点。 响应于对数据的请求，第二节点向第一节点提供响应，该第一节点将排序点传送到第一节点。
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63.发明授权公开(公告)号：US07620696B2
公开(公告)日：2009-11-17
申请号：US10761047
申请日：2004-01-20
IPC分类号： G06F15/16
CPC分类号： G06F12/0815
摘要： A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.
摘要翻译： 系统包括提供数据广播请求的第一节点。 第一节点从第一节点接收对广播请求的读冲突响应。 读取冲突响应指示第二个节点具有针对数据的未决广播读取请求。 响应于来自第一节点的广播请求，第三节点向第一节点提供所请求的数据。 第一节点填充与第一节点相关联的高速缓存中由第三节点提供的数据。
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公开(公告)号：US07409500B2
公开(公告)日：2008-08-05
申请号：US10755938
申请日：2004-01-13
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/3834 , G06F9/3842 , G06F9/3863 , G06F12/0815 , G06F2212/6022
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requests. The multi-processor system may comprise a first cache that retains cache data associated with program instructions employing data from speculative data fills, and a second cache that retains cache data associated with data from speculative data fills that have been determined to be coherent.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括具有处理器的多处理器系统，该处理器具有处理器流水线，该处理器流水线通过响应于源请求而提供的来自投机数据填充的数据执行程序指令。 多处理器系统可以包括第一高速缓存，其保存与使用来自推测数据填充的数据的程序指令相关联的高速缓存数据，以及第二高速缓存，其保存与已经被确定为相干的来自推测数据填充的数据相关联的高速缓存数据。
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65.发明授权Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss 失效多处理器系统利用并发推测源请求和响应高速缓存未命中的系统源请求公开(公告)号：US07380107B2
公开(公告)日：2008-05-27
申请号：US10756640
申请日：2004-01-13
IPC分类号： G06F15/00
CPC分类号： G06F9/383
摘要： Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a speculative data fill to a source processor in response to the speculative source request. The processor system provides a coherent data fill to the processor in response to the system source request.
摘要翻译： 公开了多处理器系统和方法，其采用推测源请求以响应于高速缓存未命中来获得推测数据填充。 在一个实施例中，源处理器响应于高速缓存未命中而产生推测源请求和系统源请求。 响应于推测源请求，至少一个处理器向源处理器提供推测数据填充。 处理器系统响应于系统源请求向处理器提供相干数据填充。
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公开(公告)号：US07240165B2
公开(公告)日：2007-07-03
申请号：US10758473
申请日：2004-01-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： A multi-processor system includes a requesting node that provides a first request for data to a home node. The requesting node being operative to provide a second request for the data to at least one predicted node in parallel with first request. The requesting node receives at least one coherent copy of the data from at least one of the home node and the at least one predicted node.
摘要翻译： 多处理器系统包括向家庭节点提供数据的第一请求的请求节点。 请求节点可操作以向第一请求并行地向至少一个预测节点提供数据的第二请求。 请求节点从家庭节点和至少一个预测节点中的至少一个接收数据的至少一个相干副本。
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公开(公告)号：US07149852B2
公开(公告)日：2006-12-12
申请号：US10761034
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , G06F12/0817 , G06F12/0831 , G06F2212/1024 , G06F2212/1044
摘要： Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.
摘要翻译： 公开了用于阻止数据响应的系统和方法。 一个系统包括目标节点，其响应于所请求数据的源广播请求提供包括所请求数据的副本的响应。 目标节点还向与请求的数据相关联的家庭节点提供阻塞消息。 如果阻塞消息与归属节点处的源广播请求匹配，则阻塞消息正在起作用，导致归属节点向源广播请求提供非数据响应。
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68.发明授权Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch 失效在采用多级节点间交换机的多处理器系统中的低延迟相互参考排序公开(公告)号：US06904465B2
公开(公告)日：2005-06-07
申请号：US09843228
申请日：2001-04-26
IPC分类号： G06F15/173 , H04L12/56 , G06F13/00 , H04L12/50
CPC分类号： H04L49/102 , G06F15/17393 , H04L49/15
摘要： A multiple-processor system in which a commit message is returned to a source processor that requests a memory access operation so as to indicate the apparent completion of the operation includes a multiple-level switch unit linking nodes that contain the processors. The switch unit includes multiple input switches each of which receives messages from multiple nodes, and a set of output switches whose inputs are the outputs of the input switches and whose outputs are the inputs of the nodes. Each switch processes messages in the order in which they are received by the switch and each output switch follows the same rule as the other output switches.
摘要翻译： 将提交消息返回给源处理器的多处理器系统，其请求存储器访问操作以指示操作的明显完成包括链接包含处理器的节点的多级交换单元。 开关单元包括多个输入开关，每个输入开关从多个节点接收消息，以及一组输出开关，其输入是输入开关的输出，其输出是节点的输入。 每个交换机按交换机接收的顺序处理消息，每个输出交换机遵循与其他输出交换机相同的规则。
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公开(公告)号：US06769057B2
公开(公告)日：2004-07-27
申请号：US09766685
申请日：2001-01-22
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842
摘要： A “data verified”, or DV, bit is included in an instruction to indicate if the instruction or a dependent instruction may be associated with the retrieved data as soon as the data is available or should instead be associated with the data after verification. If the DV bit is in a first state, e.g., not set, the system may issue instructions that use associated data as soon as the data is available. If the DV bit is in a second state, e.g., set, the system does not issue the instructions that use the data until the data is verified. The system or user sets the DV bit based on an analysis of an instruction set that includes the instruction and/or accumulated profile data from previous use or uses of the software. The DV bit is set in a LOAD instruction if the dependent user instruction is close enough in the instruction set that the user instruction is likely to issue before the data is verified and/or if the LOAD instruction is part of a relatively long chain of instructions. The DV bit may instead be set if past uses of the software indicate a complicated or time-consuming reissue operation is associated with a particular cache miss.
摘要翻译： “数据验证”或DV的位包括在指示中，以指示指示或依赖指令是否可以在数据可用时立即与检索到的数据相关联，或者应该在验证之后与数据相关联。 如果DV位处于第一状态（例如未设置），则一旦数据可用，系统就可以发出使用关联数据的指令。 如果DV位处于第二状态，例如设置，则系统不会发出使用数据的指令，直到数据被验证为止。 系统或用户基于对包括来自先前使用或使用软件的指令和/或累积简档数据的指令集的分析来设置DV位。 如果依赖用户指令在用户指令在数据被验证之前很可能发出的指令集中足够接近和/或如果LOAD指令是相对较长的指令链的一部分，则DV位被设置在LOAD指令中 。 如果软件的过去使用指示复杂或耗时的重新发行操作与特定高速缓存未命中相关联，则DV位可以被设置。
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70.发明授权Method and system for a processor to gain assured ownership of an up-to-date copy of data 失效一种处理器的方法和系统，以获得对数据的最新副本的有保证的所有权公开(公告)号：US06636948B2
公开(公告)日：2003-10-21
申请号：US09834551
申请日：2001-04-13
IPC分类号： G06F1200
CPC分类号： G06F12/0817
摘要： A performance enhancing change-to-dirty operation (CTD) is disclosed wherein contention among several processors trying to gain ownership of a block of data is obviated by arranging the CTD to always succeed. A method and a system are disclosed where a processor in a multiprocessor system having a copy of data gains assured ownership of data that the processor may then write. The method provides for the possibilities of conditions that may exist and provides a scenario that the requesting processor may have to wait for the ownership. Conditions are handled where the memory is the “owner” of the data and where other processor are requesting ownership, and where copies of the data exist at other processors. The method provides for messages to other processor having copies of the data informing them that the data is now invalid.
摘要翻译： 公开了一种性能提升的改变到脏操作（CTD），其中通过使CTD总是成功地排除尝试获得数据块所有权的若干处理器中的争用。 公开了一种方法和系统，其中具有数据副本的多处理器系统中的处理器确保处理器然后可以写入的数据的所有权。 该方法提供可能存在的条件的可能性并提供请求处理器可能必须等待所有权的情况。 在内存是数据的“所有者”以及其他处理器请求所有权的情况下以及数据的副本存在于其他处理器的情况下处理条件。 该方法向具有数据副本的其他处理器提供消息，通知他们数据现在无效。
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