公开(公告)号：US06249843B1

公开(公告)日：2001-06-19

申请号：US09368754

申请日：1999-08-05

申请人： Ravi Kumar Arimilli ,  John Steve Dodson ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  John Steve Dodson ,  Guy Lynn Guthrie

IPC分类号： G06F1200

CPC分类号： G06F9/30043 ,  G06F9/30047 ,  G06F12/0811 ,  G06F12/0831

摘要： A STORE instruction having horizontal memory hierarchy control bits is disclosed. The STORE instruction comprises an operation code field, a write-through field, and a horizontal write-through level field. The horizontal write-through level field indicates a horizontal memory level within a multi-level memory hierarchy to which the STORE operation should be applied, when the write-through field is set.

摘要翻译： 公开了具有水平存储器层级控制位的STORE指令。 STORE指令包括操作码字段，直写字段和水平写通电平字段。 当写入字段被设置时，水平写入级别字段指示应该应用STORE操作的多级存储器层级中的水平存储器级别。

公开(公告)号：US07617378B2

公开(公告)日：2009-11-10

申请号：US10425402

申请日：2003-04-28

申请人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

摘要： A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic. The TLBI register includes a sequence of bits utilized to track the completion of a TLBI issued by the processor at the other processors. Each bit corresponds to a particular processor across the system and the particular processor is able to directly set the bit in the register of a master processor once the particular processor completes a TLBI operation initiated from the master processor. The master processor is able to track completion of the TLBI operation by checking the values of each bit within its TLBI register, without requiring multi-issuance of an address-only barrier operation on the system bus.

摘要翻译： 实现TLBI协议的对称多处理器数据处理系统（SMP），使多个处理器的多个TLBI操作能够完成而不会造成延迟。 每个处理器包括与TLB和TLBI逻辑相关联的TLBI寄存器。 TLBI寄存器包括用于跟踪由处理器在其他处理器发出的TLBI的完成的位的序列。 每个位对应于跨系统的特定处理器，并且特定处理器能够在特定处理器完成从主处理器发起的TLBI操作之后直接设置主处理器的寄存器中的位。 主处理器能够通过检查其TLBI寄存器中每个位的值来跟踪完成TLBI操作，而不需要在系统总线上多次发出仅地址唯一的屏蔽操作。

公开(公告)号：US07039832B2

公开(公告)日：2006-05-02

申请号：US10313329

申请日：2002-12-05

申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.

摘要翻译： 公开了一种方法和系统，用于通过中断非测试过程的处理器执行来在安装的处理器上运行制造级测试程序。 制造级测试程序的定期执行允许处理器在正常功能操作期间不间断地进行自检，以便促进处理器和处理器作为其一部分的数据处理系统的适当维护和功能。

公开(公告)号：US06963967B1

公开(公告)日：2005-11-08

申请号：US09588508

申请日：2000-06-06

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.

摘要翻译： 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。

公开(公告)号：US06785774B2

公开(公告)日：2004-08-31

申请号：US09978362

申请日：2001-10-16

申请人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.

摘要翻译： 一种多处理器数据处理系统，包括多个处理单元，多个高速缓存，每个高速缓存与每个处理单元中的一个相关联;以及处理逻辑，响应于对一致性操作的第一系统总线响应的接收，使得 请求处理器使用超相干数据执行操作。 数据处理系统还包括逻辑，其最终返回到响应于预定条件的发生的其他处理单元的相干操作。 数据处理系统的一致性协议包括第一相关性状态，其指示在数据处理系统的系统总线上已经窥探第二处理器的第二高速缓存的共享高速缓存行内的数据的修改。 当高速缓存行处于第一相关性状态时，在系统总线上作为Z1读取发出对高速缓存行的后续请求，并且接收到两个响应中的一个。 如果对Z1读取的响应指示第一处理器应利用高速缓存行内当前可用的本地数据，则将第一相关性状态改变为第二相关性状态，其向第一处理器指示对高速缓存行的后续请求应当利用 本地缓存内的数据，不发给系统互连。 通过数据处理系统的一致性协议完成一致性状态转换到第二相关性状态。 每当为高速缓存行设置第二相关性状态并接收到请求时，将超相干数据从本地高速缓存行提供给处理器。

公开(公告)号：US06629209B1

公开(公告)日：2003-09-30

申请号：US09437185

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

公开(公告)号：US06625701B1

公开(公告)日：2003-09-23

申请号：US09437183

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1214

CPC分类号： G06F12/0811 ,  G06F12/0815

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。 优选实施例提供具有高速缓存存储命令的指示符位，其特别地指示存储还是否用作锁定释放。

公开(公告)号：US06609192B1

公开(公告)日：2003-08-19

申请号：US09588607

申请日：2000-06-06

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC分类号： G06F9312

CPC分类号： G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

摘要： Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ. Then a controller issues a load request associated with the second load instruction to memory before completion of a barrier operation associated with the barrier instruction. Alternatively, load requests are issued out-of-order with respect to the program order before or after the barrier instruction. The load request arbitration unit selects the request associated with the second load instruction before a request associated with the first load instruction, and the controller issues the request associated with the second load instruction before the request associated with the first load instruction and before issuing the barrier operation.

摘要翻译： 公开了一种多处理器数据处理系统，其针对屏障操作执行无序的负载事务。 数据处理系统包括存储器和耦合到互连的多个处理器。 至少一个处理器包括用于以程序顺序取出指令序列以执行的指令排序单元。 指令序列包括在指令序列中的第一和第二加载指令之间的第一和第二加载指令和障碍指令。 还包括在处理器中的是装载/存储单元（LSU），其具有临时缓冲与第一和第二加载指令相关联的加载请求的加载请求队列（LRQ）。 LRQ耦合到负载请求仲裁单元，该单元从LRQ中选择发出负载请求的顺序。 然后，在与障碍指令相关联的屏障操作完成之前，控制器向存储器发出与第二加载指令相关联的加载请求。 或者，负载请求在屏障指令之前或之后相对于程序顺序发出无序。 负载请求仲裁单元在与第一加载指令相关联的请求之前选择与第二加载指令相关联的请求，并且控制器在与第一加载指令相关联的请求之前发布与第二加载指令相关联的请求，并且在发布屏障之前 操作。

公开(公告)号：US06571322B2

公开(公告)日：2003-05-27

申请号：US09752863

申请日：2000-12-28

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line. Partial intervention may be achieved by issuing a request to retrieve an entire cache line, and sourcing only a first sector of the cache line in response to the request. A second sector of the same cache line may be sourced from a third cache. Other sectors may also be sourced from a system memory device of the computer system as well. Appropriate system bus codes-are utilized to transmit cache operations to the system bus and indicate which sectors of the cache line are targets of the cache operation.

摘要翻译： 一种在多处理器计算机系统中维持一致性的方法，其中每个处理单元的高速缓冲存储器具有高速缓存行。 第一高速缓存一致性状态被分配给特定高速缓存行的一个扇区，并且与第一高速缓存一致性状态不同的第二高速缓存一致性状态被分配给总高速缓存行，同时保持第一高速缓存一致性状态 部门。 第一高速缓存一致性状态可以提供第一扇区包含不与任何其它高速缓存共享的有效值（即，排他或修改状态）的指示，并且第二高速缓存一致性状态可以提供以下指示： 高速缓存行中的扇区包含与至少一个其他高速缓存（共享，最近读取或标记状态）共享的有效值。 其他一致性状态可以应用于同一高速缓存行中的其他扇区。 部分干预可以通过发出检索整个高速缓存线的请求来实现，并且仅响应于该请求仅提供高速缓存行的第一扇区。 相同高速缓存行的第二扇区可以来自第三高速缓存。 其他扇区也可以来自计算机系统的系统存储器设备。 使用适当的系统总线代码来将高速缓存操作发送到系统总线，并指示高速缓存行的哪些扇区是高速缓存操作的目标。

公开(公告)号：US06345342B1

公开(公告)日：2002-02-05

申请号：US09437177

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改的非请求（Mu）高速缓存状态，以指示保持在高速缓存行中的值已经被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用Mu状态。 读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。