公开(公告)号：US20110170327A1

公开(公告)日：2011-07-14

申请号：US12974916

申请日：2010-12-21

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G11C15/04 ,  H01L27/12

CPC classification number: G11C15/046 ,  H04L45/7453

Abstract: The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.

Abstract translation: 本发明提供一种由两个晶体管形成的可内容寻址的存储单元，其被配置为使晶体管中的一个用于存储数据位，而另一个用于存储数据位的补码。 每个晶体管具有可控制的阻挡相关晶体管的反向控制栅极。 该器件还包括比较电路，其被配置为在读取模式下操作第一和第二晶体管，同时控制每个晶体管的反向控制栅极，以便如果所提出的位和存储的位对应，则阻止通过晶体管。 然后，连接到每个晶体管的源极的源极线上的电流的存在或不存在指示所提出的位和存储的位是否相同。 本发明还提供了用于操作本发明的内容可寻址存储器单元的方法，以及具有多个本发明的可内容寻址存储单元的可内容寻址存储器。

公开(公告)号：US20110133776A1

公开(公告)日：2011-06-09

申请号：US12961293

申请日：2010-12-06

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: H03K19/173 ,  H01L27/12 ,  H03K3/01

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11807

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.

Abstract translation: 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中， 源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。 所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟 晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。 本发明还提供了操作这种半导体器件结构的方法。

公开(公告)号：US07817466B2

公开(公告)日：2010-10-19

申请号：US12130918

申请日：2008-05-30

Applicant: Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

Inventor： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

IPC: G11C11/34

CPC classification number: H01L27/105 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C2211/4016 ,  H01L21/8232 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Abstract translation: 半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。 每个单元耦合到许多控制线，允许选择和读取/写入所述单元。 所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

公开(公告)号：US20090125789A1

公开(公告)日：2009-05-14

申请号：US12140643

申请日：2008-06-17

Applicant: Richard Ferrant ,  Cedric Maufront

Inventor： Richard Ferrant ,  Cedric Maufront

IPC: G06F11/10

CPC classification number: H04L25/14 ,  H04L1/0043 ,  H04L2001/0094

Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

Abstract translation: 包括串联耦合的多个逻辑块的数据总线，每个逻辑块包括用于缓冲经由数据总线传输的至少一个数据位的至少一个缓冲器，以及至少一个逻辑块，还包括与该数据总线并联耦合的电路 至少一个缓冲器，并被布置成确定与所述至少一个数据位相关联的纠错码的第一位。

公开(公告)号：US20090086535A1

公开(公告)日：2009-04-02

申请号：US12130918

申请日：2008-05-30

Applicant: Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

Inventor： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

IPC: G11C11/34

CPC classification number: H01L27/105 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C2211/4016 ,  H01L21/8232 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Abstract translation: 半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。 每个单元耦合到许多控制线，允许选择和读取/写入所述单元。 所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

公开(公告)号：US07180801B2

公开(公告)日：2007-02-20

申请号：US10745294

申请日：2003-12-23

Applicant: Richard Ferrant ,  François Jacquet ,  Laurent Murillo

Inventor： Richard Ferrant ,  François Jacquet ,  Laurent Murillo

IPC: G11C7/00

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

Abstract translation: 一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体 ，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。 对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。

公开(公告)号：US07130206B2

公开(公告)日：2006-10-31

申请号：US10955836

申请日：2004-09-30

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C15/00 ,  G11C11/00

CPC classification number: G11C13/0004 ,  G11C15/02 ,  G11C15/046

Abstract: A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second potential value being smaller than said first potential value, and means for their switching between states exhibiting different electric resistance values. The memory cell includes a first field effect transistor and a second field effect transistor, said first and second transistors having drain-source-paths and gate electrodes, said drain-source-paths of said first and second transistors being connected in a second series connection and being connected to at least one of first current lines. The first current line is connected to a potential value level detector for sensing a potential difference as to said third potential value.

Abstract translation: 描述内容可寻址存储器单元。 在一个实施例中，内容可寻址存储器单元包括第一和第二电阻存储器元件，其以第一串联连接耦合并连接在第一电位值和小于所述第一电位值的第二电位值之间， 呈现不同电阻值的状态。 存储单元包括第一场效应晶体管和第二场效应晶体管，所述第一和第二晶体管具有漏源路径和栅电极，所述第一和第二晶体管的所述漏源极路径以第二串联连接 并且连接到第一电流线中的至少一个。 第一电流线连接到电位值电平检测器，用于感测关于所述第三电位值的电位差。

公开(公告)号：US07068533B2

公开(公告)日：2006-06-27

申请号：US10955832

申请日：2004-09-30

Applicant: Richard Ferrant ,  Arkalgud Sitaram

Inventor： Richard Ferrant ,  Arkalgud Sitaram

IPC: G11C11/00 ,  G11C11/14

CPC classification number: G11C11/15

Abstract: A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines. A plurality of resistive memory cells being disposed in a memory matrix form between said first and second current lines, said first current lines defining the columns of said memory matrix form, while said second current lines defining the rows of it, wherein each one of the resistive memory cells being connected to one of said first current lines; a plurality of selection transistors having gates and drain-source paths, each drain-source path of said selection transistors being connected to a multiplicity of the resistive memory cells of a row of said memory matrix, said drain-source paths of different selection transistors being connected to a fourth current line (SL), the gates of said selection transistors of a row of said memory matrix form being connected to one of said third current lines. It further relates to a method for sensing the resistance values of a selected resistive memory cell.

Abstract translation: 公开了一种电阻式存储单元的结构。 在一个实施例中，电阻存储单元的配置包括多条第一电流线; 多条第二电流线; 和多条第三电流线。 多个电阻存储器单元以所述第一和第二电流线之间的存储矩阵形式布置，所述第一电流线限定所述存储矩阵形式的列，而所述第二电流线限定其行，其中每个 电阻存储器单元连接到所述第一电流线之一; 具有栅极和漏极 - 源极路径的多个选择晶体管，所述选择晶体管的每个漏 - 源路径连接到所述存储矩阵的行的多个电阻存储单元，所述不同选择晶体管的所述漏 - 源路径为 连接到第四电流线（SL），所述存储矩阵形式的行的所述选择晶体管的栅极连接到所述第三电流线之一。 本发明还涉及一种用于感测所选择的电阻性存储单元的电阻值的方法。

公开(公告)号：US06934202B2

公开(公告)日：2005-08-23

申请号：US10345843

申请日：2003-01-16

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/848

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract translation: 本发明涉及一种集成电路，其包括至少一个相同元件的矩阵网络，能够至少在第一方向上被单独地寻址，并且至少包括至少对于该第一方向至少一个冗余元件，以及可逆地抑制 故障元件的操作并通过使用冗余元件来维持电路操作。 集成电路还可以包括绝对地禁止故障元件的操作并且通过使用冗余元件来维持电路操作的电路。

公开(公告)号：US20050146952A1

公开(公告)日：2005-07-07

申请号：US10745294

申请日：2003-12-23

Applicant: Richard Ferrant ,  Francois Jacquet ,  Laurent Murillo

Inventor： Richard Ferrant ,  Francois Jacquet ,  Laurent Murillo

IPC: G06F11/20 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

Abstract translation: 一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体 ，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。 对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。