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    Adaptive matrix multiplication accelerator for machine learning and deep learning applications
    62.
    发明授权
    Adaptive matrix multiplication accelerator for machine learning and deep learning applications 有权

    公开(公告)号：US11475102B2

    公开(公告)日：2022-10-18

    申请号：US16407064

    申请日：2019-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

    Coordinated in-module RAS features for synchronous DDR compatible memory
    63.
    发明授权
    Coordinated in-module RAS features for synchronous DDR compatible memory 有权

    公开(公告)号：US11294571B2

    公开(公告)日：2022-04-05

    申请号：US16819032

    申请日：2020-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

    IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    Coordinated in-module RAS features for synchronous DDR compatible memory
    68.
    发明授权
    Coordinated in-module RAS features for synchronous DDR compatible memory 有权

    公开(公告)号：US10592114B2

    公开(公告)日：2020-03-17

    申请号：US15213386

    申请日：2016-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04 ,  G11C11/406 ,  G11C5/04

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application
    70.
    发明授权
    Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application 有权

    公开(公告)号：US10318434B2

    公开(公告)日：2019-06-11

    申请号：US15905746

    申请日：2018-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

    IPC: G06F12/10 ,  G06F12/1018 ,  G06F12/0802 ,  G11C29/00 ,  G06F3/06

    Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

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