公开(公告)号：US11940922B2

公开(公告)日：2024-03-26

申请号：US18081488

申请日：2022-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna T. Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0875 ,  G06F13/12 ,  G06F13/16 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F13/124 ,  G06F13/1636 ,  G06F13/1689 ,  G06F9/3001 ,  G06F9/30098 ,  G06F2212/452

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

公开(公告)号：US10977118B2

公开(公告)日：2021-04-13

申请号：US16276304

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/00 ,  G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US20210096999A1

公开(公告)日：2021-04-01

申请号：US17121488

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna T. Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0875 ,  G06F13/16 ,  G06F13/12

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

公开(公告)号：US10915451B2

公开(公告)日：2021-02-09

申请号：US16439613

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/08 ,  G06F12/0879 ,  G11C11/417

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

公开(公告)号：US10810144B2

公开(公告)日：2020-10-20

申请号：US15285423

申请日：2016-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Young Lim ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Indong Kim

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/0868

Abstract: A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

公开(公告)号：US10223252B2

公开(公告)日：2019-03-05

申请号：US15496936

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/02 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

Abstract: A hybrid memory includes a plurality of tiles including a plurality of rows including a first row having a first type of memory cells and a second row having a second type of memory cells; a pair of bitline select signals including a bitline select signal and a bitline select bar signal that is an inverse of the bitline select signal; a wordline driver that is configured to receive an input data; a sense amplifier that is configured to output an output data; a write bitline coupled to the first row and the second row; a read bitline coupled to the first row and the second row; a wordline coupled to each of the plurality of rows; and a bitline that is coupled to the write bitline and the read bitline based on set values of the pair of bitline select signals.

公开(公告)号：US20180329651A1

公开(公告)日：2018-11-15

申请号：US15669851

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685

Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

公开(公告)号：US10114560B2

公开(公告)日：2018-10-30

申请号：US15788501

申请日：2017-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim

IPC: G06F13/00 ,  G06F3/06

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

公开(公告)号：US09971511B2

公开(公告)日：2018-05-15

申请号：US15017391

申请日：2016-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/0641 ,  G06F3/0644 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/205 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/7208

Abstract: A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.

公开(公告)号：US20180046388A1

公开(公告)日：2018-02-15

申请号：US15788501

申请日：2017-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0632 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.