公开(公告)号：US12189546B2

公开(公告)日：2025-01-07

申请号：US17872987

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi ,  Craig Hanson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US12147360B2

公开(公告)日：2024-11-19

申请号：US17872987

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi ,  Craig Hanson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20170357604A1

公开(公告)日：2017-12-14

申请号：US15285423

申请日：2016-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Young Lim ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Indong Kim

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G11C11/4094 ,  G06F12/0879 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/0891

Abstract: A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

公开(公告)号：US09837135B2

公开(公告)日：2017-12-05

申请号：US15227911

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G11C8/00 ,  G11C8/08 ,  G11C13/00

CPC classification number: G11C8/08 ,  G11C7/1018 ,  G11C8/04 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

公开(公告)号：US20170255418A1

公开(公告)日：2017-09-07

申请号：US15169609

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Craig Hanson ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies

公开(公告)号：US11029879B2

公开(公告)日：2021-06-08

申请号：US15949934

申请日：2018-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Jae-Gon Lee ,  Indong Kim

IPC: G06F3/06

Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.

公开(公告)号：US10810144B2

公开(公告)日：2020-10-20

申请号：US15285423

申请日：2016-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Young Lim ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Indong Kim

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/0868

Abstract: A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

公开(公告)号：US10114560B2

公开(公告)日：2018-10-30

申请号：US15788501

申请日：2017-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim

IPC: G06F13/00 ,  G06F3/06

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

公开(公告)号：US20180046388A1

公开(公告)日：2018-02-15

申请号：US15788501

申请日：2017-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0632 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

公开(公告)号：US12032828B2

公开(公告)日：2024-07-09

申请号：US17713228

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04 ,  G11C11/40611 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.