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    ADAPTIVE PROGRAMMING VOLTAGE FOR NON-VOLATILE MEMORY DEVICES
    61.
    发明申请
    ADAPTIVE PROGRAMMING VOLTAGE FOR NON-VOLATILE MEMORY DEVICES 审中-公开

    公开(公告)号：US20190272871A1

    公开(公告)日：2019-09-05

    申请号：US15910998

    申请日：2018-03-02

    Applicant: SanDIsk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34

    Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

    Sub-block mode for non-volatile memory
    62.
    发明授权
    Sub-block mode for non-volatile memory 有权

    公开(公告)号：US10157680B2

    公开(公告)日：2018-12-18

    申请号：US15385454

    申请日：2016-12-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Xiaochang Miao ,  Deepanshu Dutta

    IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

    Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

    NON-VOLATILE MEMORY WITH FAST MULTI-LEVEL PROGRAM VERIFY
    63.
    发明申请
    NON-VOLATILE MEMORY WITH FAST MULTI-LEVEL PROGRAM VERIFY 有权

    公开(公告)号：US20220383965A1

    公开(公告)日：2022-12-01

    申请号：US17329304

    申请日：2021-05-25

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

    Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.

    Bi-directional sensing in a memory
    65.
    发明授权
    Bi-directional sensing in a memory 有权

    公开(公告)号：US11423993B2

    公开(公告)日：2022-08-23

    申请号：US16676023

    申请日：2019-11-06

    Applicant: SanDisk Technologies LLC

    Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

    IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04

    Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

    Non-volatile memory with switchable erase methods
    67.
    发明授权
    Non-volatile memory with switchable erase methods 有权

    公开(公告)号：US11342029B2

    公开(公告)日：2022-05-24

    申请号：US17034086

    申请日：2020-09-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Ken Oowada ,  Huai-Yuan Tseng

    IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30

    Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.

    DYNAMIC STAGGERING FOR PROGRAMMING IN NONVOLATILE MEMORY
    69.
    发明申请
    DYNAMIC STAGGERING FOR PROGRAMMING IN NONVOLATILE MEMORY 有权

    公开(公告)号：US20210405891A1

    公开(公告)日：2021-12-30

    申请号：US16916620

    申请日：2020-06-30

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-Yuan Tseng

    IPC: G06F3/06

    Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

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