公开(公告)号：US20220343957A1

公开(公告)日：2022-10-27

申请号：US17526398

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20220091158A1

公开(公告)日：2022-03-24

申请号：US17308974

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungmin Jin ,  Jindo Byun ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G01R1/20 ,  G01R1/067 ,  G01R31/26

Abstract: A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

公开(公告)号：US20220083244A1

公开(公告)日：2022-03-17

申请号：US17239592

申请日：2021-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F3/06 ,  G11C7/10 ,  H04L25/49

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

公开(公告)号：US20220059156A1

公开(公告)日：2022-02-24

申请号：US17321678

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung Park ,  Younghoon Son ,  Hyunyoon Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4093 ,  G11C11/4076 ,  G06F13/16

Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

公开(公告)号：US11218343B2

公开(公告)日：2022-01-04

申请号：US17156813

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi ,  Changsik Yoo

IPC: H04L25/02 ,  H04L25/14 ,  H04L25/49

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.