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公开(公告)号：US20220076716A1
公开(公告)日：2022-03-10
申请号：US17385002
申请日：2021-07-26
发明人： Youngdo Um , Younghoon Son , Youngdon Choi , Jindo Byun , Hyunyoon Cho , Junghwan Choi
IPC分类号： G11C7/10
摘要： A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.
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公开(公告)号：US20220091158A1
公开(公告)日：2022-03-24
申请号：US17308974
申请日：2021-05-05
发明人： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
摘要： A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.
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公开(公告)号：US11115021B2
公开(公告)日：2021-09-07
申请号：US17021728
申请日：2020-09-15
发明人： Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC分类号： H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
摘要： An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号：US11615833B2
公开(公告)日：2023-03-28
申请号：US17223458
申请日：2021-04-06
发明人： Kwangseob Shin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G11C16/26 , G11C11/4091 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4099
摘要： A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.
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公开(公告)号：US11521672B2
公开(公告)日：2022-12-06
申请号：US17230519
申请日：2021-04-14
发明人： Hyeokjun Choi , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G11C7/22 , G11C11/4091 , G11C11/406 , G11C11/4076 , G11C11/408 , G11C11/4096
摘要： A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.
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公开(公告)号：US11461251B2
公开(公告)日：2022-10-04
申请号：US17326513
申请日：2021-05-21
发明人： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
摘要： A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号：US11587598B2
公开(公告)日：2023-02-21
申请号：US17385002
申请日：2021-07-26
发明人： Youngdo Um , Younghoon Son , Youngdon Choi , Jindo Byun , Hyunyoon Cho , Junghwan Choi
摘要： A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.
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公开(公告)号：US11522261B2
公开(公告)日：2022-12-06
申请号：US16730277
申请日：2019-12-30
发明人： Jindo Byun , Seonkyoo Lee , Hyunjin Kim
IPC分类号： H01P3/16 , H01P3/08 , H01L23/538 , G11C16/10 , H01P1/20
摘要： A multi-mode transmission line includes a first and second conductive layers, first and second waveguide walls, a strip line, and a blind conductor. The second conductive layer that is formed over the first conductive layer. The first waveguide wall is elongated in a first direction and is in contact with the first conductive layer and the second conductive layer in a vertical direction. The second waveguide wall is elongated in the first direction parallel to the first waveguide wall and is in contact with the first conductive layer and the second conductive layer in the vertical direction. The strip line is formed between the first and second conductive layers and between the first and second waveguide walls. The blind conductor is connected to one of the first conductive layer, the second conductive layer, the first waveguide wall, or the second waveguide wall.
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公开(公告)号：US11502687B2
公开(公告)日：2022-11-15
申请号：US17389148
申请日：2021-07-29
发明人： Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC分类号： H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
摘要： An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号：US20220075725A1
公开(公告)日：2022-03-10
申请号：US17320460
申请日：2021-05-14
发明人： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G06F12/0802 , G11C7/10 , H03K19/00 , G11C8/06 , H03K19/0185
摘要： A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.
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