-
公开(公告)号：US20240241802A1
公开(公告)日：2024-07-18
申请号：US18383350
申请日：2023-10-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung Park , Joohwan Kim , Jindo Byun , Eunseok Shin , Hyunyoon Cho , Junghwan Choi
CPC classification number: G06F11/1604 , G06F1/10 , G06F2201/805
Abstract: The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.
-
2.发明公开公开(公告)号：US20230409496A1
公开(公告)日：2023-12-21
申请号：US18242034
申请日：2023-09-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin JIN , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G06F13/1668 , H04L25/4917
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
-
公开(公告)号：US12061561B2
公开(公告)日：2024-08-13
申请号：US18242034
申请日：2023-09-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G06F13/1668 , H04L25/4917
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
-
公开(公告)号：US20220076716A1
公开(公告)日：2022-03-10
申请号：US17385002
申请日：2021-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngdo Um , Younghoon Son , Youngdon Choi , Jindo Byun , Hyunyoon Cho , Junghwan Choi
IPC: G11C7/10
Abstract: A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.
-
公开(公告)号：US11914416B2
公开(公告)日：2024-02-27
申请号：US17737575
申请日：2022-05-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung Park , Joohwan Kim , Jindo Byun , Eunseok Shin , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.
-
Patent Agency Ranking
6.发明授权公开(公告)号：US11804838B2
公开(公告)日：2023-10-31
申请号：US17751148
申请日：2022-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung Park , Joohwan Kim , Jindo Byun , Eunseok Shin , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC: H03K17/693 , H03K19/20 , G11C11/4076 , G11C11/4093 , H03M9/00
CPC classification number: H03K17/693 , H03K19/20 , G11C11/4076 , G11C11/4093 , H03M9/00
Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.
-
公开(公告)号：US11669448B2
公开(公告)日：2023-06-06
申请号：US17320460
申请日：2021-05-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC: G06F12/0802 , G11C7/10 , G11C8/06 , H03K19/00 , H03K19/0185
CPC classification number: G06F12/0802 , G11C7/1048 , G11C8/06 , H03K19/0027 , H03K19/018521
Abstract: A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.
-
公开(公告)号：US20220091158A1
公开(公告)日：2022-03-24
申请号：US17308974
申请日：2021-05-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
Abstract: A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.
-
公开(公告)号：US11115021B2
公开(公告)日：2021-09-07
申请号：US17021728
申请日：2020-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC: H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
-
公开(公告)号：US11789879B2
公开(公告)日：2023-10-17
申请号：US17903240
申请日：2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G06F13/1668 , H04L25/4917
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.016 seconds)
