公开(公告)号：US11776628B2

公开(公告)日：2023-10-03

申请号：US17350770

申请日：2021-06-17

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kazuki Isozumi ,  Parth Amin

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

公开(公告)号：US20230253056A1

公开(公告)日：2023-08-10

申请号：US17665267

申请日：2022-02-04

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/14 ,  G11C16/28 ,  G11C16/102 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.

公开(公告)号：US20230197172A1

公开(公告)日：2023-06-22

申请号：US17557492

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3454 ,  G11C16/3409 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

公开(公告)号：US20230186998A1

公开(公告)日：2023-06-15

申请号：US17551640

申请日：2021-12-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/32 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

公开(公告)号：US20230154550A1

公开(公告)日：2023-05-18

申请号：US17529722

申请日：2021-11-18

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/3404 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08 ,  G11C16/0433

Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.

公开(公告)号：US20230129421A1

公开(公告)日：2023-04-27

申请号：US17511988

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/04

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory cells that is individually adapted for each of the plurality of groupings. The control means then applies the unique select gate voltage to the drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the drain-side select gate transistor of the selected ones of the strings during a memory operation.

公开(公告)号：US20230125748A1

公开(公告)日：2023-04-27

申请号：US17511966

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Xiaochen Zhu

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.

公开(公告)号：US20230102668A1

公开(公告)日：2023-03-30

申请号：US17487665

申请日：2021-09-28

Applicant: SanDisk Technologies LLC.

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means coupled to the plurality of word lines and the strings. The control means is configured to identify the at least one edge word line. The control means is also configured to periodically apply a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

公开(公告)号：US11615839B2

公开(公告)日：2023-03-28

申请号：US17368727

申请日：2021-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11565 ,  H01L25/065 ,  H01L27/11582

Abstract: In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.

公开(公告)号：US20230050955A1

公开(公告)日：2023-02-16

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.