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119 条记录 (耗时 0.026 秒)

    Ring-topology based multiprocessor data access bus
    63.
    发明授权
    Ring-topology based multiprocessor data access bus 失效
    基于环形拓扑的多处理器数据访问总线

    公开(公告)号：US07043579B2

    公开(公告)日：2006-05-09

    申请号：US10313741

    申请日：2002-12-05

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  John Samuel Liberty ,  Peichun Peter Liu

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  John Samuel Liberty ,  Peichun Peter Liu

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4243

    摘要： The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.

    摘要翻译： 本发明提供一种数据访问环。 数据访问环具有多个附接的处理器单元（APU）和与每个APU相关联的本地存储器。 数据访问环具有耦合到多个APU的数据命令环。 数据命令环可用于将多个APU中的一个APU的选择的标记携带到APU。 数据访问环还具有耦合到多个APU的数据地址环。 数据地址环还可用于在数据命令环携带多个APU中的一个APU的选择的标记之后，将所选择的APU的存储位置的标记携带预定数量的时钟周期。 数据访问环还具有耦合到多个APU的数据传送环。 在数据地址环将存储器位置的标记传送到所选择的APU之后，数据传送环可用于将数据传送到与APU相关联的存储器位置的数据到预定数量的时钟周期。

    Latch type sense amplifier method and apparatus
    64.
    发明授权
    Latch type sense amplifier method and apparatus 失效
    锁存型读出放大器的方法和装置

    公开(公告)号：US06898135B2

    公开(公告)日：2005-05-24

    申请号：US10606587

    申请日：2003-06-26

    申请人： Toru Asano ,  Sang Hoo Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

    发明人： Toru Asano ,  Sang Hoo Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/1051

    摘要： Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.

    摘要翻译： 公开了一种克服与流水线存储器电路相关的读出路径中的信号延迟问题的装置和方法。 闩锁型读出放大器（SA）用于在读出之前的一个周期中的预充电状态期间接收存储单元逻辑电平。 因此，SA可以在读取锁存时钟周期期间快速提供输出信号。 SA输出通过一个动态使能的逻辑电路被传送到一个锁存电路，用于保持接收逻辑值用于下一个时钟周期。

    Multiprocessor with pair-wise high reliability mode, and method therefore
    65.
    发明授权
    Multiprocessor with pair-wise high reliability mode, and method therefore 失效
    具有成对的高可靠性模式的多处理器和方法

    公开(公告)号：US06772368B2

    公开(公告)日：2004-08-03

    申请号：US09734117

    申请日：2000-12-11

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Ravi Nair ,  Steven Douglas Posluszny

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Ravi Nair ,  Steven Douglas Posluszny

    IPC分类号： G06F1116

    CPC分类号： G06F11/1641 ,  G06F9/30189 ,  G06F9/3861 ,  G06F9/3885 ,  G06F11/1407 ,  G06F2201/845

    摘要： In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic. The compare unit signals the commit logic in each respective processor that the possibility has been eliminated of a calculation interrupt arising for that instruction, once the compare unit receives signatures for corresponding versions of a result, but only if the signatures match. This permits the commit logic to commit the result. If the signatures do not match, the compare unit signals the commit logic that the corresponding instruction has faulted. The commit logic permits instructions prior to the faulting instruction in program order to continue execution, but initiates flushing of results that were produced by the faulting instruction and at least some instructions subsequent in program order to the faulting instruction.

    摘要翻译： 在一个实施例中，多处理装置包括第一处理器和第二处理器。 每个处理器都有自己的数据和指令高速缓存来支持独立操作。 在正常模式下，处理器独立地执行单独的指令流。 每个处理器具有相应的签名生成器。 该系统还包括耦合到签名生成器的比较单元。 在高可靠性模式下，两个处理器执行相同的指令流。 也就是说，每个处理器计算流中的指令的结果的版本。 响应于各自的版本，相应的签名生成器向比较单元提供签名，从而可以检测到故障指令。 在另一方面，每个处理器具有其各自的提交逻辑。 一旦比较单元接收到相应版本的结果的签名，但只有当签名匹配时，比较单元才会发信号通知每个相应处理器中的提交逻辑已经消除了该指令产生的计算中断的可能性。 这允许提交逻辑提交结果。 如果签名不匹配，则比较单元向提交逻辑发出相应指令发生故障的信号。 提交逻辑允许以程序顺序执行故障指令之前的指令继续执行，但是启动由故障指令产生的结果和程序顺序中的至少一些指令冲洗到故障指令。

    Latching dynamic logic structure, and integrated circuit including same
    66.
    发明授权
    Latching dynamic logic structure, and integrated circuit including same 有权
    闭锁动态逻辑结构，集成电路包括相同

    公开(公告)号：US06744282B1

    公开(公告)日：2004-06-01

    申请号：US10401327

    申请日：2003-03-27

    申请人： Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi ,  James Douglas Warnock ,  Dieter Wendel

    发明人： Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi ,  James Douglas Warnock ,  Dieter Wendel

    IPC分类号： H03K1900

    CPC分类号： H03K19/0963

    摘要： A latching dynamic logic structure is disclosed including a static logic interface, a dynamic logic gate, and a static latch. The static logic interface receives a data signal, a select signal, and a clock signal, and produces a first intermediate signal such that when the select signal is active, the first intermediate signal is dependent upon the data signal for a period of time following a clock signal transition. The dynamic logic gate discharges a dynamic node following the clock signal transition dependent upon the first intermediate signal. The static latch produces an output signal assuming one of two logic levels following the clock signal transition, and assuming the other logic level in the event the dynamic node is discharged. A scan-testing-enabled version of the latching dynamic logic structure is described, as is an integrated circuit including the latching dynamic logic structure.

    摘要翻译： 公开了一种闭锁动态逻辑结构，其包括静态逻辑接口，动态逻辑门和静态锁存器。 静态逻辑接口接收数据信号，选择信号和时钟信号，并产生第一中间信号，使得当选择信号有效时，第一中间信号取决于数据信号一段时间 时钟信号转换。 动态逻辑门在取决于第一中间信号的时钟信号转换之后放电动态节点。 静态锁存器产生一个输出信号，假定在时钟信号转换之后有两个逻辑电平之一，并且假定动态节点放电的另一个逻辑电平。 描述了锁定动态逻辑结构的扫描测试功能版本，以及包括锁存动态逻辑结构的集成电路。

    Multiple level cache memory with overlapped L1 and L2 memory access
    69.
    发明授权
    Multiple level cache memory with overlapped L1 and L2 memory access 失效
    具有重叠的L1和L2存储器访问的多级高速缓存

    公开(公告)号：US6138208A

    公开(公告)日：2000-10-24

    申请号：US59000

    申请日：1998-04-13

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  David Meltzer ,  Joel Abraham Silberman

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  David Meltzer ,  Joel Abraham Silberman

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0884

    摘要： A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.

    摘要翻译： 提供对多个高速缓存级别的同时或重叠访问以减少对于较高级别的高速缓存未命中的延迟损失的方法。 处理器发出值（数据或指令）的请求，并且在确定高速缓存的较高级别是否发生了该值的高速缓存未命中之前被转发到高速缓存的较低级。 在其中较低级别是L2高速缓存的实施例中，L2高速缓存可以将该值直接提供给处理器。 地址解码器在高速缓存的较高级并行操作以满足多个同时的存储器请求。 其中一个地址（由基于来自高速缓存的较高级别的命中/未命中信息的优先级逻辑选择）由多路复用器选通到高速缓存的较低级的多个存储器阵列字线驱动器。 可以立即解码地址中的一些不需要虚拟到实际转换的位。

    Multifunctional macro
    70.
    发明授权
    Multifunctional macro 失效
    多功能宏

    公开(公告)号：US6065028A

    公开(公告)日：2000-05-16

    申请号：US716818

    申请日：1996-09-16

    申请人： Sang Hoo Dhong ,  Joel Abraham Silberman

    发明人： Sang Hoo Dhong ,  Joel Abraham Silberman

    IPC分类号： G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  G06F7/38

    CPC分类号： G06F9/3001 ,  G06F9/30029 ,  G06F9/30032

    摘要： Fixed point instructions ADD, ROTATE, COMPARE-TO-ZERO, AND, OR and COUNT-LEADING-ZEROS are each performable in one circuit or macro. Such fixed point instructions may be implemented within an execution unit in a microprocessor, microcontroller, or digital signal processor.

    摘要翻译： 固定点指令ADD，ROTATE，COMPARE-TO-ZERO，AND，OR和COUNT-LEADING-ZEROS都可以在一个电路或宏中执行。 这样的固定点指令可以在微处理器，微控制器或数字信号处理器的执行单元内实现。