公开(公告)号：US07380099B2

公开(公告)日：2008-05-27

申请号：US10956164

申请日：2004-09-30

申请人： Sanu K. Mathew ,  Mark A. Anders ,  Sarvesh H. Kulkarni ,  Ram Krishnamurthy

发明人： Sanu K. Mathew ,  Mark A. Anders ,  Sarvesh H. Kulkarni ,  Ram Krishnamurthy

IPC分类号： G06F12/00

CPC分类号： G06F7/507 ,  G06F7/508

摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

摘要翻译： 一种用于地址产生电路的方法和装置。 在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。 一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。 随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。 在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。 描述和要求保护其他实施例。

公开(公告)号：US07362621B2

公开(公告)日：2008-04-22

申请号：US10676276

申请日：2003-09-30

申请人： Bhaskar P. Chatterjee ,  Steven K. Hsu ,  Ram Krishnamurthy

发明人： Bhaskar P. Chatterjee ,  Steven K. Hsu ,  Ram Krishnamurthy

IPC分类号： G11C7/10

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C2207/104

摘要： A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.

摘要翻译： 寄存器文件包括多电平多路复用器输出电路，其耦合到耦合到所述全局位线跟踪和驱动信号迹线的全局位跟踪和保持器电路。 寄存器文件还具有耦合到所述保持器电路的解码器电路，以选择性地将驱动信号迹线与所述全局位线分离。

公开(公告)号：US20070147158A1

公开(公告)日：2007-06-28

申请号：US11321366

申请日：2005-12-28

申请人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： G11C5/14

CPC分类号： G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227

摘要： Disclosed herein are memory circuit embodiments to have spatially encoded data.

摘要翻译： 这里公开了具有空间编码数据的存储器电路实施例。

公开(公告)号：US07190286B2

公开(公告)日：2007-03-13

申请号：US11314236

申请日：2005-12-22

申请人： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I. Ismail

发明人： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I. Ismail

IPC分类号： H03M7/46 ,  H03M7/00

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

摘要翻译： 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US20060186924A1

公开(公告)日：2006-08-24

申请号：US11411647

申请日：2006-04-26

申请人： Steven Hsu ,  Mark Anders ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Mark Anders ,  Ram Krishnamurthy

IPC分类号： H03K19/0175

CPC分类号： H03K3/356113 ,  H03K3/012

摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

公开(公告)号：US20060132187A1

公开(公告)日：2006-06-22

申请号：US11018011

申请日：2004-12-20

申请人： James Tschanz ,  Ram Krishnamurthy ,  Siva Narendra ,  Vivek De

发明人： James Tschanz ,  Ram Krishnamurthy ,  Siva Narendra ,  Vivek De

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： In some embodiments, a circuit is provided that comprises a dynamic circuit and a body bias circuit. The dynamic circuit has a keeper transistor. The body bias circuit is coupled to the keeper transistor and is configured to body bias the keeper transistor in accordance with a leakage associated with the dynamic circuit. Other embodiments are disclosed herein.

摘要翻译： 在一些实施例中，提供了包括动态电路和体偏置电路的电路。 动态电路具有保持晶体管。 体偏置电路耦合到保持器晶体管，并且被配置为根据与动态电路相关联的泄漏来对保持器晶体管进行偏置。 本文公开了其它实施例。

公开(公告)号：US20060044013A1

公开(公告)日：2006-03-02

申请号：US10924906

申请日：2004-08-25

申请人： Steven Hsu ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Ram Krishnamurthy

IPC分类号： H03K19/0175

CPC分类号： H03K3/356156

摘要： A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.

摘要翻译： 逻辑电路通过驱动具有不同电源电压的电路的部分来执行内部电平转换功能。 在一个实施例中，第一和第二级存储电路以不同的电源电压驱动。 在另一个实施例中，用第一电源电压驱动第一和第二级存储电路，并且以第二电源电压驱动耦合到第一级存储电路的反相器。 在这两种情况下，可以通过时钟信号的不同状态来控制对存储电路的数据传输。 逻辑电路可以是触发器电路，锁存电路或另一种类型的电路。

公开(公告)号：US07002389B2

公开(公告)日：2006-02-21

申请号：US10732791

申请日：2003-12-09

申请人： Atila Alvandpour ,  Ram Krishnamurthy

发明人： Atila Alvandpour ,  Ram Krishnamurthy

IPC分类号： H03K3/12

CPC分类号： H03K17/164

摘要： A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

摘要翻译： 具有经历高到低转换的接收信号的第一反相阈值的静态接收机，以及经历低到高转换的接收信号的第二反相阈值，其中第一反转阈值大于第二反转阈值。 一个实施例包括静态接收器，pFET和nFET，其中当在接收器的输入端口处接收到高电平到低电平的转换时，pFET耦合到输入端口，以便有助于提高反转阈值， 并且当在输入端口处接收到低电平到高电平的转换时，nFET耦合到输入端口，以便有助于降低反转阈值。 描述和要求保护其他实施例。

公开(公告)号：US20050285624A1

公开(公告)日：2005-12-29

申请号：US10880751

申请日：2004-06-29

申请人： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

IPC分类号： H03K3/356 ,  H03K19/0175

CPC分类号： H03K3/356113 ,  H03K3/356147 ,  H03K3/356156

摘要： A device comprising a receiving circuit to receive an input signal, a voltage level converting circuit and a biasing circuit. The receiving circuit including an output and a first latch circuit coupled to a first supply node. The voltage level converting circuit includes a second latch circuit coupled to a second supply node, the second latch circuit including cross-coupled logic gates connected between first and second circuit nodes. The second supply node has a voltage level different from the first supply node. The biasing circuit has an input coupled to the receiving circuit output, and also has first and second outputs connectable to bias the first and second circuit nodes of the second latch circuit to complementary logic states based on the receiving circuit output.

摘要翻译： 一种装置，包括用于接收输入信号的接收电路，电压电平转换电路和偏置电路。 接收电路包括耦合到第一电源节点的输出端和第一锁存电路。 电压电平转换电路包括耦合到第二电源节点的第二锁存电路，第二锁存电路包括连接在第一和第二电路节点之间的交叉耦合逻辑门。 第二供电节点具有与第一供电节点不同的电压电平。 偏置电路具有耦合到接收电路输出的输入，并且还具有可连接的第一和第二输出，以便基于接收电路输出将第二锁存电路的第一和第二电路节点偏置为互补逻辑状态。

公开(公告)号：US20050148102A1

公开(公告)日：2005-07-07

申请号：US10748833

申请日：2003-12-30

申请人： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

发明人： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

IPC分类号： H01L21/00

CPC分类号： H03K19/018521 ,  H03K3/356139 ,  H04L25/028 ,  H04L25/0292

摘要： According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

摘要翻译： 根据一些实施例，提供了一种用于接收全摆幅输入信号，将全摆幅输入信号转换为低摆幅信号并传输低回转信号的静态低摆幅驱动器电路，以及动态 接收器电路来接收低摆动信号并将低摆幅信号转换成全摆幅信号。 还可以提供耦合到驱动器电路和接收器电路的互连，互连不包括中继器并且接收来自驱动器电路的低摆动信号并且将低回转信号发送到接收器电路。