公开(公告)号：US20250031449A1

公开(公告)日：2025-01-23

申请号：US18374877

申请日：2023-09-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  G02F1/133 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28 ,  H01L29/10 ,  H01L29/786 ,  H03K19/003

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

公开(公告)号：US12100366B2

公开(公告)日：2024-09-24

申请号：US18212752

申请日：2023-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3648 ,  G09G3/2096 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/043

Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

公开(公告)号：US12062310B2

公开(公告)日：2024-08-13

申请号：US18092468

申请日：2023-01-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G11C19/00 ,  G02F1/133 ,  G06F3/038 ,  G09G3/14 ,  G09G3/36 ,  G11C19/28 ,  H01L27/12 ,  G09G3/20 ,  G09G3/3291

CPC classification number: G09G3/14 ,  G02F1/133 ,  G06F3/038 ,  G09G3/3677 ,  G09G3/3688 ,  G11C19/28 ,  H01L27/124 ,  G09G3/20 ,  G09G3/3291 ,  G09G3/36 ,  G09G3/3614 ,  G09G3/3674 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2320/043

Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.

公开(公告)号：US12002529B2

公开(公告)日：2024-06-04

申请号：US18205000

申请日：2023-06-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G11C19/18 ,  G09G3/36 ,  G09G3/3266

CPC classification number: G11C19/184 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2320/02 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/023

Abstract: In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

公开(公告)号：US11955192B2

公开(公告)日：2024-04-09

申请号：US18206702

申请日：2023-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/18 ,  G09G3/3266 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

CPC classification number: G11C19/184 ,  G09G3/3266 ,  G09G3/3677 ,  H01L27/1225 ,  H01L29/7869 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2340/0492

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

公开(公告)号：US20230395034A1

公开(公告)日：2023-12-07

申请号：US18234752

申请日：2023-08-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  H01L23/528 ,  G02F1/1345 ,  G02F1/1362 ,  H01L29/786 ,  G11C19/28

CPC classification number: G09G3/3674 ,  H01L23/528 ,  G02F1/13454 ,  G02F1/136286 ,  G09G3/3677 ,  H01L29/786 ,  G11C19/28 ,  G02F2201/124 ,  H01L27/1214

Abstract: A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

公开(公告)号：US11735598B2

公开(公告)日：2023-08-22

申请号：US16654721

申请日：2019-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/00 ,  H01L27/12 ,  H01L29/786 ,  H01L29/10 ,  G11C19/28 ,  G09G3/20 ,  H03K19/003 ,  G09G3/3266 ,  G09G3/36 ,  G02F1/133

CPC classification number: H01L27/124 ,  G09G3/20 ,  G11C19/28 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H03K19/00346 ,  G02F1/13306 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

公开(公告)号：US11620962B2

公开(公告)日：2023-04-04

申请号：US17862464

申请日：2022-07-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G11C19/28 ,  H01L27/12 ,  G11C19/18

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

公开(公告)号：US11501728B2

公开(公告)日：2022-11-15

申请号：US17206746

申请日：2021-03-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20

Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

公开(公告)号：US11373609B2

公开(公告)日：2022-06-28

申请号：US17110502

申请日：2020-12-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20 ,  H03K17/04

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.