公开(公告)号：US12294031B2

公开(公告)日：2025-05-06

申请号：US18422699

申请日：2024-01-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28 ,  H01L21/477 ,  H01L27/12 ,  H01L29/786

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

公开(公告)号：US12230638B2

公开(公告)日：2025-02-18

申请号：US18216963

申请日：2023-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Atsushi Umezaki

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786

Abstract: A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs.

公开(公告)号：US12191322B2

公开(公告)日：2025-01-07

申请号：US18437410

申请日：2024-02-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G11C19/00 ,  H01L29/786 ,  H03B1/00 ,  H03K3/00 ,  H03K17/687

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

公开(公告)号：US12159880B2

公开(公告)日：2024-12-03

申请号：US18640136

申请日：2024-04-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/3266 ,  G11C19/28 ,  H01H71/02 ,  H01H71/10 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1345 ,  H01L27/13 ,  H01L29/423 ,  H10K59/121 ,  H10K59/131

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

公开(公告)号：US12100368B2

公开(公告)日：2024-09-24

申请号：US18370427

申请日：2023-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hajime Kimura

IPC: G09G3/36 ,  G02F1/133 ,  G02F1/1362 ,  G11C19/28 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC classification number: G09G3/3677 ,  G02F1/13306 ,  G02F1/136286 ,  G09G3/3648 ,  G11C19/28 ,  G11C19/287 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/42356 ,  H01L29/7869 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08

Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

公开(公告)号：US12094884B2

公开(公告)日：2024-09-17

申请号：US18089708

申请日：2022-12-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Atsushi Umezaki

IPC: H01L27/13 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  H10K59/131

CPC classification number: H01L27/1225 ,  G02F1/13624 ,  H01L27/124 ,  H01L29/7869 ,  H10K59/131

Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced.

公开(公告)号：US12027532B2

公开(公告)日：2024-07-02

申请号：US18080096

申请日：2022-12-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/00 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/325 ,  G09G3/36 ,  G11C19/28 ,  H01L27/12 ,  H03K3/356 ,  H03K19/003 ,  H03K19/20 ,  G09G3/3258 ,  G09G3/3266

CPC classification number: H01L27/124 ,  G02F1/13624 ,  G09G3/20 ,  G09G3/325 ,  G09G3/3674 ,  G11C19/28 ,  G11C19/287 ,  H01L27/1214 ,  H03K3/356 ,  H03K3/356104 ,  H03K19/00369 ,  H03K19/20 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2330/021

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

公开(公告)号：US11916150B2

公开(公告)日：2024-02-27

申请号：US17946116

申请日：2022-09-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/20 ,  G09G3/36 ,  H01L29/786 ,  G11C19/28 ,  H01L21/477 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G09G3/20 ,  G09G3/3648 ,  G11C19/28 ,  H01L21/477 ,  H01L27/127 ,  H01L27/1255 ,  G09G2300/04 ,  G09G2310/0275

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

公开(公告)号：US11901377B2

公开(公告)日：2024-02-13

申请号：US18096045

申请日：2023-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  H01L29/786 ,  G09G3/14 ,  H03B1/00 ,  H03K3/00 ,  G09G3/32 ,  G09G3/36 ,  H03K17/687 ,  G11C19/00

CPC classification number: H01L27/1255 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G11C19/00 ,  H01L29/7869 ,  H03B1/00 ,  H03K3/00 ,  H03K17/6871 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/021

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

公开(公告)号：US11893950B2

公开(公告)日：2024-02-06

申请号：US18100108

申请日：2023-01-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20 ,  H03K17/04

CPC classification number: G09G3/3648 ,  G09G3/20 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/043 ,  G09G2352/00 ,  H03K17/04

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.