公开(公告)号：US20130062614A1

公开(公告)日：2013-03-14

申请号：US13591140

申请日：2012-08-21

申请人： Naveen Tipirneni ,  Sameer Pendharkar

发明人： Naveen Tipirneni ,  Sameer Pendharkar

IPC分类号： H01L29/70 ,  H01L21/20 ,  H01L29/20

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： An apparatus includes an enhancement mode transistor having multiple Group III-V layers above a substrate and a gate above the Group III-V layers. The gate includes multiple layers of material that form at least a portion of a thyristor. The multiple layers of material may include a first p-type layer of material, an n-type layer of material on the first p-type layer, and a second p-type layer of material on the n-type layer. The multiple layers of material may also include a p-type layer of material, an n-type layer of material on the p-type layer, and a Schottky metal layer on the n-type layer. The enhancement mode transistor may represent a high electron mobility transistor (HEMT) or a heterostructure field effect transistor (HFET).

摘要翻译： 一种装置包括在衬底上方具有多个III-V层的增强型晶体管和在III-V层以上的栅极。 栅极包括形成晶闸管的至少一部分的多层材料。 多层材料可以包括第一p型材料层，第一p型层上的n型材料层和n型层上的第二p型材料层。 多层材料还可以包括p型层材料，p型层上的n型材料层和n型层上的肖特基金属层。 增强型晶体管可以表示高电子迁移率晶体管（HEMT）或异质结构场效应晶体管（HFET）。

公开(公告)号：US08304303B2

公开(公告)日：2012-11-06

申请号：US12273850

申请日：2008-11-19

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

摘要翻译： 提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和 晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。

公开(公告)号：US20120104497A1

公开(公告)日：2012-05-03

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片 交界处 在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与 排水或身体区域。 在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

公开(公告)号：US20110111569A1

公开(公告)日：2011-05-12

申请号：US13006589

申请日：2011-01-14

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US20110076822A1

公开(公告)日：2011-03-31

申请号：US12961885

申请日：2010-12-07

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

公开(公告)号：US07893499B2

公开(公告)日：2011-02-22

申请号：US12417810

申请日：2009-04-03

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L29/66

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US20100252882A1

公开(公告)日：2010-10-07

申请号：US12417810

申请日：2009-04-03

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US20100241413A1

公开(公告)日：2010-09-23

申请号：US12406423

申请日：2009-03-18

申请人： Yong Liu ,  Keith R. Green ,  Sameer Pendharkar

发明人： Yong Liu ,  Keith R. Green ,  Sameer Pendharkar

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A processor with a computer program product embodied thereon for modeling an LDMOS transistor having a drift region is provided. Characteristic behavior of a CMOS transistor with its body coupled to its source is generated, and characteristic behavior of a resistor is generated, where the resistor is coupled to the drain of the CMOS transistor. Then to account for impact ionization, an impact ionization current for electrons in the drift region an impact ionization current for holes in the drift region are calculated.

摘要翻译： 提供了一种其上实施有用于对具有漂移区域的LDMOS晶体管进行建模的计算机程序产品的处理器。 产生其主体与其源极耦合的CMOS晶体管的特性，并且产生电阻器的特性，其中电阻器耦合到CMOS晶体管的漏极。 然后考虑到冲击电离，计算漂移区域中电子的冲击电离电流对漂移区中空穴的电离电流。

公开(公告)号：US07602019B2

公开(公告)日：2009-10-13

申请号：US11408692

申请日：2006-04-20

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/72

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/41 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/66659 ,  H03K19/00384

摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.

摘要翻译： 晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。 晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。 在第一半导体区域和第二半导体区域之间存在界面。 晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。 还描述了一种混合技术电路。

公开(公告)号：US20090068804A1

公开(公告)日：2009-03-12

申请号：US12273850

申请日：2008-11-19

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

摘要翻译： 提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和 晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。