公开(公告)号：US20110076822A1

公开(公告)日：2011-03-31

申请号：US12961885

申请日：2010-12-07

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

公开(公告)号：US08426281B2

公开(公告)日：2013-04-23

申请号：US12961885

申请日：2010-12-07

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

公开(公告)号：US20100314670A1

公开(公告)日：2010-12-16

申请号：US12789040

申请日：2010-05-27

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

IPC分类号： H01L29/78 ,  H01L29/04

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7846

摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.

摘要翻译： 在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。

公开(公告)号：US08754497B2

公开(公告)日：2014-06-17

申请号：US12789040

申请日：2010-05-27

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7846

摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.

摘要翻译： 在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。

公开(公告)号：US07847351B2

公开(公告)日：2010-12-07

申请号：US12101608

申请日：2008-04-11

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L29/76

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 一种包括源极和漏极区域以及绝缘区域和板状结构的半导体器件。 源区和漏区在半导体衬底上或半导体衬底中。 绝缘区域位于或位于半导体衬底中并位于源区和漏区之间。 绝缘区域具有薄层和厚层。 厚层包括彼此分离并且跨越源极和漏极区域之间的长度延伸的多个绝缘条。 板结构位于源区和漏区之间，其中板结构位于薄层和厚层的部分上，板结构具有一个或多个导电带，其直接位于多个绝缘中的单独绝缘层上 条纹。

公开(公告)号：US20090256199A1

公开(公告)日：2009-10-15

申请号：US12101608

申请日：2008-04-11

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 一种包括源极和漏极区域以及绝缘区域和板状结构的半导体器件。 源区和漏区在半导体衬底上或半导体衬底中。 绝缘区域位于或位于半导体衬底中并位于源区和漏区之间。 绝缘区域具有薄层和厚层。 厚层包括彼此分离并且跨越源极和漏极区域之间的长度延伸的多个绝缘条。 板结构位于源区和漏区之间，其中板结构位于薄层和厚层的部分上，板结构具有一个或多个导电带，其直接位于多个绝缘中的单独绝缘层上 条纹。

公开(公告)号：US09806190B2

公开(公告)日：2017-10-31

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/861 ,  H01L27/06

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

公开(公告)号：US08853029B2

公开(公告)日：2014-10-07

申请号：US13188162

申请日：2011-07-21

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

公开(公告)号：US20120104497A1

公开(公告)日：2012-05-03

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片 交界处 在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与 排水或身体区域。 在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

公开(公告)号：US20110111569A1

公开(公告)日：2011-05-12

申请号：US13006589

申请日：2011-01-14

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。