公开(公告)号：US06829722B2

公开(公告)日：2004-12-07

申请号：US09821326

申请日：2001-03-29

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F1100

CPC classification number: G06F11/2733 ,  G06F11/1487

Abstract: A method of processing memory, suitable for loading an executable object code compiled from a source code into the memory that includes defective memory cells. At first, set up a plurality of pre-compiled object codes that correspond to a source code, each pre-compiled object code having at least a skipped-code-address range. Then, test the memory and locate the defective addresses therein. According to the result of the test, the code-loading system selects an executable object that has the matching skipped-code-address range from the pre-compiled object codes, and loads the executable code into the memory. Since the skipped-code-address range covers the defective addresses in the memory, the defective memory cells in the memory won't affect the operation of loading a program.

Abstract translation: 一种处理存储器的方法，适用于将从源代码编译的可执行目标代码加载到包括有缺陷存储器单元的存储器中。 首先，设置与源代码相对应的多个预编译对象代码，每个预编译对象代码至少具有跳过代码地址范围。 然后，测试存储器并找到其中的缺陷地址。 根据测试结果，代码加载系统从预编译对象代码中选择具有匹配的跳过代码地址范围的可执行对象，并将可执行代码加载到存储器中。 由于跳过代码地址范围覆盖存储器中的缺陷地址，所以存储器中的有缺陷的存储单元不会影响加载程序的操作。

公开(公告)号：US06691246B1

公开(公告)日：2004-02-10

申请号：US09690327

申请日：2000-10-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F1100

CPC classification number: G06F11/1417

Abstract: A method of processing a partially defective memory for loading a machine code program into a memory device that includes at least one defective memory cell. At first the machine code program is scanned. In addition, a movable code block between two break points, which is ready to be loaded to the defective memory cell of the memory device, is determined. Then the block code is moved to a memory space between a first address and a second address in which there is no defective memory cell. Finally, the moved code block should be linked in the execution sequence with the unmoved portion of the machine code program and the addressing references correlated between the moved code block and the unmoved portion of the machine code program should be modified is and corrected. The resulting machine code program can be properly loaded and executable.

Abstract translation: 一种处理用于将机器代码程序加载到包括至少一个有缺陷的存储器单元的存储器件中的部分缺陷存储器的方法。 首先扫描机器代码程序。 此外，确定准备加载到存储装置的有缺陷的存储单元的两个断点之间的可移动代码块。 然后将块代码移动到第一地址和第二地址之间的存储器空间，其中没有有缺陷的存储器单元。 最后，移动的代码块应该在执行顺序中与机器代码程序的不动部分链接，并且应该修改移动的代码块和机器代码程序的不动部分之间相关的寻址引用。 所得到的机器代码程序可以正确加载并执行。

公开(公告)号：US06653998B2

公开(公告)日：2003-11-25

申请号：US09740223

申请日：2000-12-19

Applicant: Shi-Tron Lin ,  Yung-Peng Hwang

Inventor： Shi-Tron Lin ,  Yung-Peng Hwang

IPC: G09G336

CPC classification number: G09G3/2011 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2330/021 ,  H03M1/765

Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2. A plurality of blocking transistors can positioned between the input and selected digital signal lines, with at least one of the digital signal lines being coupled to a gate of each of the blocking transistors for controlling each of the blocking transistors. A level-shifter can also be positioned between selected active regions for one or more digital signal line.

公开(公告)号：US06414361B2

公开(公告)日：2002-07-02

申请号：US09754145

申请日：2001-01-05

Applicant: Shyh-Chyi Wong ,  Shi-Tron Lin

Inventor： Shyh-Chyi Wong ,  Shi-Tron Lin

IPC: H01L2976

CPC classification number: H01L29/66651 ,  H01L21/76224 ,  H01L21/823878

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract translation: 集成半导体器件包括具有埋入浅沟槽隔离结构的衬底和设置在衬底上的外延层和埋入的浅沟槽隔离结构。 外延层包括浅沟槽隔离结构，其在衬底中的埋入的浅沟槽隔离结构上延伸，以基本上减少衬底中的漏电流以防止器件闭锁。

公开(公告)号：US06370655B1

公开(公告)日：2002-04-09

申请号：US09174676

申请日：1998-10-19

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F1120

CPC classification number: G06F9/445 ,  G06F11/1433

Abstract: A computer system is provided that loads a computer program, in a reverse order, into a memory device having one or more defective memory cells. The program is organized into code modules with each code module including at least one complete instruction, or data block. The last code module of the program is loaded first into the last or highest addresses of the address space allocated in the memory for the program. Thereafter, the code module preceding the last loaded code module of the program is loaded into the addresses preceding the previously-loaded addresses. The subsequent code modules are loaded into successively lower memory addresses in a reverse fashion until the first code module of the program is loaded into memory. As each code module, or the codes that make up the code module, are loaded, each loaded memory address is checked for a defective cell. A JUMP instruction is created and inserted into the original program code preceding the defective memory address to bypass any defective memory cell without interrupting the intended operation of the instruction steps that are loaded into the memory. In addition, a JUMP instruction is inserted into the memory start address so that a processor is forced to begin execution at the memory address containing the first byte of the first code module. Certain byte codes that include referenced addresses are then modified to correct any address-referencing that may be changed due to the insertion of the JUMP instructions, and then loaded into the appropriate addresses in the memory.

Abstract translation: 提供了一种计算机系统，其以相反的顺序将计算机程序加载到具有一个或多个有缺陷的存储器单元的存储器件中。 该程序被组织成代码模块，每个代码模块包括至少一个完整指令或数据块。 程序的最后一个代码模块首先加载到程序存储器中分配的地址空间的最后或最高地址。 此后，程序的最后加载的代码模块之前的代码模块被加载到先前加载的地址之前的地址中。 随后的代码模块以相反的方式加载到连续较低的存储器地址中，直到程序的第一代码模块被加载到存储器中。 由于每个代码模块或构成代码模块的代码都被加载，所以检查每个加载的存储器地址是否有缺陷的单元。 创建JUMP指令并将其插入到缺陷存储器地址之前的原始程序代码中，以绕过任何有缺陷的存储单元，而不会中断加载到存储器中的指令步骤的预期操作。 另外，JUMP指令被插入到存储器起始地址中，使处理器被迫在包含第一代码模块的第一个字节的存储器地址开始执行。 然后修改包括引用地址的某些字节码，以纠正由于插入JUMP指令而可能改变的任何地址引用，然后加载到存储器中的相应地址。

公开(公告)号：US06304127B1

公开(公告)日：2001-10-16

申请号：US09126197

申请日：1998-07-30

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F724

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transient negative voltage pump circuit pumps the ESD voltage to a negative voltage. The negative voltage with the ESD voltage are used for early triggering of an SCR structure on the integrated circuit. In one version of the present invention, a pn junction diode of the SCR device is used as part of the negative voltage pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract translation: 瞬态负电压泵电路将ESD电压泵送到负电压。 具有ESD电压的负电压用于早期触发集成电路上的SCR结构。 在本发明的一个版本中，SCR装置的pn结二极管用作负电压泵电路的一部分。 这样可以节省布局面积，同时提高ESD性能。 本发明改进了用于在ESD事件期间保护电源总线或IC引脚的SCR ESD保护电路的ESD性能。

公开(公告)号：US06297686B1

公开(公告)日：2001-10-02

申请号：US09321849

申请日：1999-05-28

Applicant: Shi-Tron Lin ,  Yung-Chow Peng

Inventor： Shi-Tron Lin ,  Yung-Chow Peng

IPC: H03K301

CPC classification number: H03K19/01707 ,  H01L27/092 ,  H01L29/78609 ,  H03K19/0016

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract translation: 对于集成电路中的MOSFET的低电压和高速操作，向源节点施加小的电压，从而导致源极结的轻微的正向偏压，从而降低其阈值电压。 由于源节点偏置和物体效应的组合效应，阈值电压的降低大于施加的源极电压的绝对值。 通过简单地将偏置电压施加到身体（井），可以提高性能。 可以使用事件的检测来仅在需要时将性能提升应用于集成电路中的关键路径。 当检测到逻辑事件确定信号在此后不久将传播通过关键路径时，关键路径中的电路元件的源节点偏置可以及时调整以提高速度。 然而，当没有信号通过关键路径时，源保持在另一个潜力，以便在不提升速度时节省功率。

公开(公告)号：US06246122B1

公开(公告)日：2001-06-12

申请号：US09345128

申请日：1999-07-06

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2348

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the internal circuit of the IC connected to wired pins of the IC package against ESD damage due to ESD stress in neighboring no-connect pins. The ESD protective device includes an ESD protective unit coupled to the power bus and a bonding pad coupled between this ESD protective device and the no-connect pin. The ESD protective unit causes ESD stress applied to the no-connect pin to be diverted to the power bus, thus preventing ESD transfer between a no-connect pin and an active pin, which could damage the internal circuit.

Abstract translation: 一种用于保护集成电路（IC）封装免受静电放电损坏的ESD保护装置。 ESD保护装置保护连接到IC封装的有线引脚的IC的内部电路，防止由于相邻不连接引脚中的ESD应力而导致的ESD损坏。 ESD保护装置包括耦合到电源总线的ESD保护单元和耦合在该ESD保护装置和无连接引脚之间的接合焊盘。 ESD保护单元会使施加到无连接引脚的ESD应力转移到电源总线，从而防止无连接引脚和有源引脚之间的ESD传输，这可能会损坏内部电路。

公开(公告)号：US06233130B1

公开(公告)日：2001-05-15

申请号：US09126200

申请日：1998-07-30

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H02H900

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L29/87

Abstract: A transient voltage-pump circuit pumps the ESD voltage to a higher voltage. The pumped-high transient voltage is used for early triggering of an SCR. In one version of the present invention, a pn junction of the SCR device is used as part of the voltage-pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract translation: 瞬态电压泵电路将ESD电压泵送到更高的电压。 泵浦高瞬态电压用于SCR的早期触发。 在本发明的一个版本中，SCR器件的pn结用作电压 - 泵电路的一部分。 这样可以节省布局面积，同时提高ESD性能。 本发明改进了用于在ESD事件期间保护电源总线或IC引脚的SCR ESD保护电路的ESD性能。

公开(公告)号：US6107681A

公开(公告)日：2000-08-22

申请号：US45327

申请日：1998-03-20

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/60 ,  H01L23/48

CPC classification number: H01L23/60 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.