公开(公告)号：US07674720B2

公开(公告)日：2010-03-09

申请号：US12131214

申请日：2008-06-02

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

摘要翻译： 公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。 在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫 并且在开口中外延生长硅。 由于底切产生的负斜率，硅片堆积层错误大大减少。

公开(公告)号：US20090181508A1

公开(公告)日：2009-07-16

申请号：US12014934

申请日：2008-01-16

申请人： Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

发明人： Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A method forms a gate stack over a channel region of a substrate and then forms disposable spacers on sides of the gate stack. Trenches are then recessed in regions of the substrate not protected by the gate stack and the disposable spacers. Carbon-doped Silicon lattice structures are then formed in the trenches. During the forming of the Carbon-doped Silicon lattice structures Carbon atoms can be positioned in any substitutional sites within the lattice structures. The Carbon-doped Silicon lattice structures are then amorphized by implantation of an amorphizing species. An annealing process then recrystallizes the amorphized regions by solid-phase epitaxy regrowth to form the source and drain regions. During the annealing, a majority of Carbon atoms are substitutionally incorporated into a Silicon lattice of the source and drain regions to provide tensile stress to the channel region.

摘要翻译： 一种方法在衬底的通道区域上形成栅极堆叠，然后在栅极叠层的侧面上形成一次性间隔物。 沟槽然后凹陷在不被栅极堆叠和一次性间隔件保护的衬底的区域中。 然后在沟槽中形成碳掺杂的硅晶格结构。 在形成碳掺杂硅晶格结构期间，碳原子可以位于晶格结构内的任何取代位置。 然后通过植入非晶化物质将碳掺杂的硅晶格结构非晶化。 退火工艺然后通过固相外延再生长再结晶非晶化区域以形成源区和漏区。 在退火期间，大多数碳原子被替代地并入到源极和漏极区域的硅晶格中，以向沟道区域提供拉伸应力。

公开(公告)号：US07528050B2

公开(公告)日：2009-05-05

申请号：US12115106

申请日：2008-05-05

申请人： Judson R. Holt ,  Qiqing C. Ouyang

发明人： Judson R. Holt ,  Qiqing C. Ouyang

IPC分类号： H01L21/46

CPC分类号： H01L29/78 ,  H01L21/76254 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7846

摘要： The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.

摘要翻译： 本发明提供了一种半导体结构，其包括绝缘体（SOI）上的高性能场效应晶体管（FET），其绝缘体是预选几何形状的应力诱导材料。 这种结构可以实现单轴应力的性能提高，并且通道中的应力不依赖于局部触点的布局设计。 广义而言，本发明涉及一种包括上半导体层和底半导体层的半导体结构，其中所述上半导体层通过具有预选的应力诱导绝缘体在至少一个区域中与所述底部半导体层分离 几何形状，所述应力诱导绝缘子在上半导体层上施加应变。

公开(公告)号：US07485524B2

公开(公告)日：2009-02-03

申请号：US11425542

申请日：2006-06-21

申请人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.

摘要翻译： 本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。 这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。 优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面 。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。 具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

公开(公告)号：US07405436B2

公开(公告)日：2008-07-29

申请号：US11029797

申请日：2005-01-05

申请人： Dureseti Chidambarrao ,  Judson R. Holt ,  Meikei Ieong ,  Oiging C. Ouyang ,  Siddhartha Panda

发明人： Dureseti Chidambarrao ,  Judson R. Holt ,  Meikei Ieong ,  Oiging C. Ouyang ,  Siddhartha Panda

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

摘要翻译： 提供了具有改进的载流子迁移率的半导体结构。 半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。 本发明还提供了制造该方法的方法。 一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道 。

公开(公告)号：US20080116484A1

公开(公告)日：2008-05-22

申请号：US11561496

申请日：2006-11-20

申请人： Henry K. Utomo ,  Judson R. Holt ,  Haining S. Yang

发明人： Henry K. Utomo ,  Judson R. Holt ,  Haining S. Yang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78687

摘要： A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.

摘要翻译： 提供一种半导体器件，其包括位于氧化物层之上的第一硅层和第二硅层上的氧化物层，其中氧化物层位于第一硅层和第二硅层之间。 第一硅层和第二硅层包含相同的晶体取向。 所述器件还包括在所述第一硅层上的分级锗层，其中所述分级锗层接触间隔物和所述第一硅层并且不接触所述氧化物层。 分级锗层的下部包含比分级锗层的上部更高浓度的锗，其中分级锗层的顶表面缺少锗。

公开(公告)号：US20080026516A1

公开(公告)日：2008-01-31

申请号：US11459730

申请日：2006-07-25

申请人： Ashima B. Chakravarti ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

发明人： Ashima B. Chakravarti ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

IPC分类号： H01L21/8234

CPC分类号： H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

公开(公告)号：US20080006854A1

公开(公告)日：2008-01-10

申请号：US11425542

申请日：2006-06-21

申请人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7848 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.

摘要翻译： 本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。 这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。 优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面 。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。 具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

公开(公告)号：US20070275510A1

公开(公告)日：2007-11-29

申请号：US11420318

申请日：2006-05-25

申请人： Huajie Chen ,  Judson R. Holt ,  Rangarajan Jagannathan ,  Wesley C. Natzle ,  Michael R. Sievers ,  Richard S. Wise

发明人： Huajie Chen ,  Judson R. Holt ,  Rangarajan Jagannathan ,  Wesley C. Natzle ,  Michael R. Sievers ,  Richard S. Wise

IPC分类号： H01L21/8232 ,  H01L21/8234 ,  H01L21/335

CPC分类号： H01L29/66636 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

摘要翻译： 公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。 蚀刻半导体层以形成切割栅极介电层的凹部。 低能量植入物形成晕轮。 然后，执行COR预清洁，并且通过外延沉积填充凹部。 外延可以被原位掺杂或随后植入以形成源/漏扩展。 或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。 在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。 或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。

公开(公告)号：US09006052B2

公开(公告)日：2015-04-14

申请号：US12901733

申请日：2010-10-11

申请人： Judson R. Holt ,  Viorel C. Ontalus ,  Keith H. Tabakman

发明人： Judson R. Holt ,  Viorel C. Ontalus ,  Keith H. Tabakman

IPC分类号： H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78654 ,  H01L29/66553 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

摘要： A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.

摘要翻译： 一种方法包括在沉积在基底上的应力层中形成的沟槽中形成应力Si层。 受应力的Si层形成器件的有源沟道区。 该方法还包括在由应力Si层形成的有源沟道区中形成栅极结构。