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    (Meth)acrylic ester of alkenylene glycols and the use thereof
    61.
    发明申请
    (Meth)acrylic ester of alkenylene glycols and the use thereof 失效
    （甲基）亚烷基二醇的丙烯酸酯及其用途

    公开(公告)号：US20060247377A1

    公开(公告)日：2006-11-02

    申请号：US10558996

    申请日：2004-06-04

    Applicant: Ulrich Riegel ,  Thomas Daniel ,  Matthias Weismantel ,  Mark Elliott ,  Rudiger Funk ,  Reinhold Schwalm

    Inventor： Ulrich Riegel ,  Thomas Daniel ,  Matthias Weismantel ,  Mark Elliott ,  Rudiger Funk ,  Reinhold Schwalm

    IPC: C08L67/02 ,  C07C67/26

    CPC classification number: C07C69/54 ,  C07C67/08

    Abstract: The present invention relates to novel (meth)acrylic esters of polyalkoxylated glycols of the formula where AO is independently at each instance is —O—CHR3-CHR4- or —CHR3-CHR4-O— where R3 and R4 are independently H, linear or branched C1-C8-alkyl, p1 is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, or 35, p2 is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, or 35, n is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 447, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, R1 and R2 are independently H or CH3, wherein there is at least one AO in (AO)p1 and also at least one AO in (AO)p2 where R3 and R4 are not both H at one and the same time, a simplified process for preparing these esters and use of reaction mixtures thus obtainable.

    Abstract translation: 本发明涉及下式的聚烷氧基化二醇的（甲基）丙烯酸酯：其中AO各自独立地为-O-CHR 3 -CHR 4 - 或-CHR 3 -CHR 4 -O-，其中R 3和R 4独立地为H，直链或 支链C 1 -C 8 - 烷基，p 1为1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21 ，22,23,24,25,26,27,28,29,30,31,32,33,34或35中，p2分别为1,2,3,4,5,6,7,8,9,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34或35， 10，11，12，13，14，15，16，17，18，19，20，21，22，23，24，25，26，27，28，29，30，31，32，33，34， 或35，n为1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 ，24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,447,48 ，49，50，51，52，53，54，55，56，57，58，59，60，61，62，63，64，65，66，67，68，69，70，，71，72，73 ，74，75，76，77，78，79，80，81，82，83，84，85，86，87，88，89，90，91，92，93，94，95，96，97，98 ，99,100，R 1和R 2独立地为H或CH 3，其中存在至少一个AO （AO）p 1和（AO）p2中的至少一个AO，其中R3和R4不同时为一个，制备这些酯的简化方法和使用由此获得的反应混合物。

    Efficient implementation of first-in-first-out memories for multi-processor systems
    67.
    发明授权
    Efficient implementation of first-in-first-out memories for multi-processor systems 有权
    高效地实现多处理器系统的先进先出存储器

    公开(公告)号：US06615296B2

    公开(公告)日：2003-09-02

    申请号：US09881512

    申请日：2001-06-14

    Applicant: Thomas Daniel ,  Anil Gupta

    Inventor： Thomas Daniel ,  Anil Gupta

    IPC: G06F1320

    CPC classification number: G06F15/167

    Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

    Abstract translation: 为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。 第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。 当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。 此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。 在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

    Register reservation method for fast context switching in microprocessors
    68.
    发明授权
    Register reservation method for fast context switching in microprocessors 失效
    微处理器快速上下文切换的注册预约方法

    公开(公告)号：US5987258A

    公开(公告)日：1999-11-16

    申请号：US883137

    申请日：1997-06-27

    Applicant: Thomas Daniel ,  Anil Gupta

    Inventor： Thomas Daniel ,  Anil Gupta

    IPC: G06F9/46 ,  G06F9/45

    CPC classification number: G06F9/462

    Abstract: Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.

    Abstract translation: 微处理器主程序及其中断处理例程以高级编程语言（如C）编写。每个编译单独编译，每个编译调用编译器选项，命令编译器在编译代码中不使用给定的一组寄存器。 然后对编译的中断代码进行后处理，以通过访问给定的寄存器组来替换对第一组寄存器的访问。 结果是当主程序和中断处理程序都用C编写时，每个编译代码使用不同的寄存器。 这允许从主程序到中断处理程序的上下文切换，并且在异常处理期间几乎没有传统上与上下文切换寄存器保存和恢复操作相关联的开销。

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