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61.发明申请Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation 审中-公开包含嵌入式应变诱导半导体材料的晶体管中的应变增强合金种类冷凝公开(公告)号：US20120161203A1
公开(公告)日：2012-06-28
申请号：US13196318
申请日：2011-08-02
IPC分类号： H01L21/336 , H01L21/225 , H01L29/78 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/165 , H01L21/18 , H01L29/161 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration.
摘要翻译： 在需要高压缩应变的晶体管中，可以通过应用锗冷凝技术来增加锗含量。 在一些说明性实施例中，在基于选择性外延生长技术获得的硅/锗材料的存在下进行氧化工艺，从而在将锗驱动到有源区的下部区域的同时越来越多地氧化硅种， 这最终导致锗浓度增加。
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62.发明授权Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process 有权制造具有升高的源极/漏极区域的晶体管器件以适应金属硅化物形成过程中的消耗的方法公开(公告)号：US09490344B2
公开(公告)日：2016-11-08
申请号：US13345922
申请日：2012-01-09
IPC分类号： H01L21/02 , H01L21/334 , H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。
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63.发明授权Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations 有权在28nm低功率/高性能技术上的PMOS器件的中间原位掺杂SiGe结，使用硅氧化物封装，早期晕圈和延伸注入公开(公告)号：US08703578B2
公开(公告)日：2014-04-22
申请号：US13482410
申请日：2012-05-29
IPC分类号： H01L21/76
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0883 , H01L29/0847 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
摘要翻译： 提供具有PMOS eSiGe源极/漏极区域的HKMG器件。 实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并且在第二HKMG栅堆叠的相对侧形成深源极/漏极区域 第二个HKMG门栈。
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64.发明授权Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same 有权增加硅锗层中的锗浓度的方法和包括其的半导体器件的方法公开(公告)号：US08574981B2
公开(公告)日：2013-11-05
申请号：US13101659
申请日：2011-05-05
IPC分类号： H01L21/02
CPC分类号： H01L21/02587 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/823807 , H01L21/84 , H01L29/1054 , H01L29/161 , H01L29/66431 , H01L29/66651 , H01L29/7781 , H01L29/7833
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度 在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。
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公开(公告)号：US08524563B2
公开(公告)日：2013-09-03
申请号：US13345457
申请日：2012-01-06
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
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66.发明授权Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy 有权通过沟道半导体合金的合金种类的不对称浓度分布来驱动场效应晶体管的电流增加公开(公告)号：US08501601B2
公开(公告)日：2013-08-06
申请号：US13239672
申请日：2011-09-22
IPC分类号： H01L21/425
CPC分类号： H01L29/1054 , H01L21/2254 , H01L21/26506 , H01L21/26586 , H01L29/66636 , H01L29/66659
摘要： When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.
摘要翻译： 当形成复杂的晶体管时，可以提供沟道区，使得沟道材料的带隙能量的梯度可导致优异的电荷载流子速度。 例如，可以沿着沟道长度方向实现锗，碳等的浓度梯度，从而获得更高的晶体管性能。
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67.发明申请High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials 审中-公开基于占位符材料优越平面度的替代门法形成的高K金属栅电极结构公开(公告)号：US20120196425A1
公开(公告)日：2012-08-02
申请号：US13354613
申请日：2012-01-20
申请人： Thilo Scheiper , Andy Wei , Stefan Flachowsky , Jan Hoentschel
发明人： Thilo Scheiper , Andy Wei , Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L29/785 , H01L21/823828 , H01L29/513 , H01L29/66545 , H01L29/66795
摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures.
摘要翻译： 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过在诸如多晶硅材料的占位符材料的沉积之后实施至少一个平坦化工艺，并且在实际上 图案化栅电极结构。
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68.发明申请Drive Current Increase in Field Effect Transistors by Asymmetric Concentration Profile of Alloy Species of a Channel Semiconductor Alloy 有权通过半导体合金合金种类的不对称浓度曲线驱动场效应晶体管的电流增加公开(公告)号：US20120193708A1
公开(公告)日：2012-08-02
申请号：US13239672
申请日：2011-09-22
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/2254 , H01L21/26506 , H01L21/26586 , H01L29/66636 , H01L29/66659
摘要： When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.
摘要翻译： 当形成复杂的晶体管时，可以提供沟道区，使得沟道材料的带隙能量的梯度可导致优异的电荷载流子速度。 例如，可以沿着沟道长度方向实现锗，碳等的浓度梯度，从而获得更高的晶体管性能。
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69.发明申请Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material 审中-公开基于应变通道半导体材料的三维晶体管中的应变工程公开(公告)号：US20120025312A1
公开(公告)日：2012-02-02
申请号：US13164928
申请日：2011-06-21
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/823821 , H01L21/823807 , H01L29/66795 , H01L29/7843 , H01L29/7848 , H01L29/785
摘要： In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors.
摘要翻译： 在诸如finFET的三维晶体管配置中，半导体鳍片的至少一个表面可以设置有应变半导体材料，其可以沿着当前流动方向具有明显的单轴应变分量。 应变半导体材料可以在任何适当的制造阶段提供，例如，在实际构图半导体鳍片之前和/或在图案化半导体鳍片之后，从而在调整三维晶体管的整体特性方面提供优异的性能和灵活性。
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70.发明授权Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures 有权在包括高k金属栅电极结构的晶体管中降低阈值电压宽度依赖性公开(公告)号：US09048336B2
公开(公告)日：2015-06-02
申请号：US13186813
申请日：2011-07-20
申请人： Thilo Scheiper , Jan Hoentschel , Steven Langdon
发明人： Thilo Scheiper , Jan Hoentschel , Steven Langdon
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/265 , H01L21/28 , H01L29/10 , H01L21/84 , H01L27/12 , H01L29/51
CPC分类号： H01L21/26506 , H01L21/266 , H01L21/2822 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/517
摘要： Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
摘要翻译： 复杂晶体管的性能和/或均匀性可以通过在形成复杂的高k金属栅电极结构之前在晶体管的有源区中引入碳物种来增强。 例如，在选择性地形成用于P沟道晶体管的阈值调节半导体材料之后，可以通过离子注入将碳物质并入P沟道晶体管和N沟道晶体管的有源区，而N的有源区 通道晶体管仍然被掩蔽。
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