公开(公告)号：US20210200707A1

公开(公告)日：2021-07-01

申请号：US17135129

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F21/45

Abstract: In some examples, a method includes receiving a transaction at an inbound port, the transaction including a requester identification (ID), a traffic class, and a peripheral component interconnect express (PCIe) address. The method includes providing an attribute based at least in part on the traffic class. The method includes providing a context ID based on the attribute and the requester ID. The method includes accessing a region of memory responsive to the transaction, the region of memory corresponding to the context ID.

公开(公告)号：US20210170945A1

公开(公告)日：2021-06-10

申请号：US16709548

申请日：2019-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat SAGAR ,  Mihir Narendra MODY ,  Anthony Joseph LELL ,  Gregory Raymond SHURTZ

IPC: B60R1/00 ,  H04N5/225

Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

公开(公告)号：US20210165744A1

公开(公告)日：2021-06-03

申请号：US17171185

申请日：2021-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20190114786A1

公开(公告)日：2019-04-18

申请号：US15784285

申请日：2017-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hetul SANGHVI ,  Mihir Narendra MODY ,  Mike LACHMAYR ,  Anish REGHUNATH ,  Rajat SAGAR

IPC: G06T7/223 ,  G06T7/246

CPC classification number: G06T7/223 ,  G06T7/248 ,  G06T7/269 ,  G06T2207/10016

Abstract: An optical flow system includes a binary mask generation circuit and an optical flow circuit. The binary mask generation circuit is configured to receive a plurality of points of interest from a captured image that contains an array of pixels arranged as rows and columns and includes width lines that correspond to the rows and height lines that correspond to the columns. The binary mask generation circuit is also configured to generate a binary mask based on the plurality of points of interest. The binary mask includes a representation of a subset of the plurality of points of interest. The optical flow circuit is configured to receive the binary mask and generate an optical flow map of the subset of the plurality of points of interest.

公开(公告)号：US20180255303A1

公开(公告)日：2018-09-06

申请号：US15970497

申请日：2018-05-03

Applicant: Texas Instruments Incorporated

Inventor： Hrushikesh Tukaram GARUD ,  Mihir Narendra MODY ,  Soyeb NAGORI

IPC: H04N19/147 ,  H04N19/117 ,  H04N19/82 ,  H04N19/176 ,  H04N19/182 ,  H04N19/149

CPC classification number: H04N19/147 ,  H04N19/117 ,  H04N19/149 ,  H04N19/176 ,  H04N19/182 ,  H04N19/82

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

公开(公告)号：US20180192020A1

公开(公告)日：2018-07-05

申请号：US15395001

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Shashank DABRAL ,  Rajasekhar ALLU ,  Niraj NANDAN

IPC: H04N9/77 ,  H04N9/04

CPC classification number: H04N9/045 ,  G06T1/20 ,  H04N9/04515 ,  H04N9/67 ,  H04N2209/046

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.