公开(公告)号：US20240037028A1

公开(公告)日：2024-02-01

申请号：US18082693

申请日：2022-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar CHITNIS ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA ,  Sriramakrishnan GOVINDARAJAN ,  Mohd FAROOQUI ,  Shailesh GHOTGALKAR

IPC: G06F12/02

CPC classification number: G06F12/0292

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

公开(公告)号：US20230376442A1

公开(公告)日：2023-11-23

申请号：US18363035

申请日：2023-08-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: G06F13/42 ,  G06F13/40 ,  G06F12/1027

CPC classification number: G06F13/4247 ,  G06F13/4022 ,  G06F12/1027 ,  G06F2213/0038 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

公开(公告)号：US20200242048A1

公开(公告)日：2020-07-30

申请号：US16256821

申请日：2019-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20200210205A1

公开(公告)日：2020-07-02

申请号：US16700254

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Denis Roland BEAUDOIN ,  Gregory Raymond SHURTZ ,  Santhanakrishnan Badri NARAYANAN ,  Mark Adrian BRYANS ,  Mihir Narendra MODY ,  Jason A.T. JONES ,  Jayant THAKUR

IPC: G06F9/4401 ,  H04L12/721 ,  H04L12/741 ,  H04L12/931 ,  H04L12/823 ,  G06F13/28

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20240345970A1

公开(公告)日：2024-10-17

申请号：US18756055

申请日：2024-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY ,  Jason A.T. Jones

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F12/10 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A peripheral proxy subsystem provides routing mechanisms to allow multiple hosts to communicate with multiple functions, physical and virtual, of a single root I/O virtualization (SR-IOV) peripheral, which may include a physical function and a plurality of virtual functions associated with the physical function. The peripheral proxy subsystem, which may be embodied as a controller, includes a first endpoint interface; a second endpoint interface; and a single root controller interface configured to couple to the SR-IOV peripheral. The controller is configured to be able to present through the single root controller interface: a first subset of the plurality of virtual functions through a first cloned instance of the physical function at the first endpoint interface; and a second subset of the plurality of virtual functions through a second cloned instance of the physical function at the second endpoint interface.

公开(公告)号：US20220138058A1

公开(公告)日：2022-05-05

申请号：US17463232

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F11/14 ,  G06F11/34 ,  G06F11/30

Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.

公开(公告)号：US20210209036A1

公开(公告)日：2021-07-08

申请号：US17073925

申请日：2020-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY ,  Jason A.T. JONES

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/42

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

公开(公告)号：US20200210256A1

公开(公告)日：2020-07-02

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Charles Lance FUOCO ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  William A. MILLS ,  Gregory Raymond SHURTZ ,  Amritpal Singh MUNDRA

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/455

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US20230350811A1

公开(公告)日：2023-11-02

申请号：US18346309

申请日：2023-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20230326002A1

公开(公告)日：2023-10-12

申请号：US18333151

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Veeramanikandan RAJU ,  Niraj NANDAN ,  Samuel Paul VISALLI ,  Jason A.T. JONES ,  Kedar Satish CHITNIS ,  Gregory Raymond SHURTZ ,  Prithvi Shankar YEYYADI ANANTHA ,  Sriramakrishnan GOVINDARAJAN

IPC: G06T7/00 ,  G06T1/20 ,  G06T3/40 ,  G05B23/02

CPC classification number: G06T7/0002 ,  G06T1/20 ,  G06T3/40 ,  H04N17/00 ,  G06T7/97 ,  G06T2207/10016 ,  G05B23/0259

Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.