公开(公告)号：US20200302995A1

公开(公告)日：2020-09-24

申请号：US16892932

申请日：2020-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: G11C11/412 ,  H01L27/11

Abstract: SRAM arrays are provided. In each SRAM cell arranged in a column of cell array, a pull-down transistor and a pass-gate transistor are formed in P-type well region. A pull-up transistor is formed in N-type well region. At least one well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the P-type well region. A first distance between the active region of the N-well strap structure and the P-type well region is greater than a second distance between an active region of the pull-up transistor and the P-type well region.

公开(公告)号：US20200286892A1

公开(公告)日：2020-09-10

申请号：US16881804

申请日：2020-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/092 ,  H01L27/11 ,  H01L23/532 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/66

Abstract: Semiconductor structures are provided. A first logic cell includes a plurality of first transistors over a substrate. Each first transistor includes a first gate electrode across a first channel region. The first gate electrode is electrically connected to a first conductive line of the metal layer through a first contact in a first dielectric layer and a first via in a second dielectric layer over the first dielectric layer. A second logic cell includes a plurality of second transistors over the substrate. Each second transistor includes a second gate electrode across a second channel region. The second gate electrode is electrically connected to a second conductive line of the metal layer directly through a second via in the first and second dielectric layers. The first transistors are surrounded by dummy gate electrodes, and the second transistors are surrounded by dummy gate dielectrics.

公开(公告)号：US20200273851A1

公开(公告)日：2020-08-27

申请号：US16282679

申请日：2019-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L29/161 ,  H03K19/0948 ,  H03K19/00

Abstract: Semiconductor structures are provided. A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height, and a plurality of metal lines parallel to each other in a metal layer. The second cell height is different than the first cell height. The first logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells, and the metal lines inside the first logic cells are wider than the metal lines inside the second logic cells.

公开(公告)号：US20190164967A1

公开(公告)日：2019-05-30

申请号：US15853542

申请日：2017-12-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/092 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a first circuit and a second circuit. The first circuit includes a first gate, a first drain, and a first source. The second circuit includes a second gate, a second drain, and a second source. The first drain and the first source of the first circuit include a first doping material with a first concentration. A gate pitch and a gate critical dimension of the first gate of the first circuit are the same as a gate pitch and a gate critical dimension of the second gate of the second circuit. The second drain and the second source of the second circuit include a second doping material with a second concentration, wherein the first concentration is different from the second concentration.

公开(公告)号：US20180315853A1

公开(公告)日：2018-11-01

申请号：US15600919

申请日：2017-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Dian-Sheg YU ,  Ren-Fen TSUI ,  Jhon-Jhy LIAW

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/28114 ,  H01L21/3105 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.

公开(公告)号：US20180301559A1

公开(公告)日：2018-10-18

申请号：US15489841

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/78 ,  H01L23/528 ,  H01L27/02 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7851 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

Abstract: A semiconductor device is provided, which includes a substrate, a gate and a gate contact. The substrate has a well region, which has a source, a drain and a channel region extending between the source and the drain. The gate is on the well region and extends across the channel region. The gate contact is directly on the gate and vertically overlaps with the channel region. The gate contact has a strip shape of which a ratio of a length to a width is at least 2. The gate contact includes a gate conductive plug and a gate contact dielectric. The gate conductive plug directly contacts the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and has a frame shape. A dielectric constant of the gate contact dielectric is substantially greater than 4.9.

公开(公告)号：US20180286884A1

公开(公告)日：2018-10-04

申请号：US15475391

申请日：2017-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/118 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238

Abstract: A device includes first circuit cells. Each of the first circuit cells includes isolation transistors, a first type transistor, a second type transistor, and a first gate contact. The isolation transistors are arranged adjacent to another one circuit cell of the plurality of first circuit cells. The first type transistor includes a first gate electrode. The second type transistor includes a second gate electrode, in which the second gate electrode is disposed with respect to the first gate electrode. The first gate contact is coupled between the first gate electrode and the second gate electrode.