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    Trench gate high voltage transistor for embedded memory
    61.
    发明授权
    Trench gate high voltage transistor for embedded memory 有权

    公开(公告)号：US11189628B2

    公开(公告)日：2021-11-30

    申请号：US16404983

    申请日：2019-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Cheng Wu ,  Alexander Kalnitsky ,  Chien-Hung Chang

    IPC: H01L27/1157 ,  H01L27/11575 ,  H01L29/06 ,  H01L21/033 ,  H01L29/423 ,  H01L21/28

    Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated into a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A first logic device comprises a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed on the first logic gate dielectric within the logic device trench. By arranging the first logic gate electrode within the logic device trench, metal layer loss and the resulted sheet resistance and threshold voltage variations and mismatch issues caused by the subsequent planarization process can be improved.

    NVM memory HKMG integration technology
    65.
    发明授权
    NVM memory HKMG integration technology 有权

    公开(公告)号：US10811426B2

    公开(公告)日：2020-10-20

    申请号：US16393159

    申请日：2019-04-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Cheng Wu ,  Chien-Hung Chang

    IPC: H01L27/11573 ,  H01L29/423 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11536

    Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region disposed adjacent to the memory region. The memory region comprises a non-volatile memory (NVM) device having a control gate electrode and a select gate electrode disposed between two neighboring source/drain regions over a substrate. The control gate electrode and the select gate electrode comprise polysilicon. The logic region comprises a logic device including a metal gate electrode disposed between two neighboring source/drain regions over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.

    BOUNDARY DESIGN TO REDUCE MEMORY ARRAY EDGE CMP DISHING EFFECT
    67.
    发明申请
    BOUNDARY DESIGN TO REDUCE MEMORY ARRAY EDGE CMP DISHING EFFECT 审中-公开

    公开(公告)号：US20200098778A1

    公开(公告)日：2020-03-26

    申请号：US16695505

    申请日：2019-11-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Cheng Wu ,  Chien-Hung Chang

    IPC: H01L27/11575 ,  H01L21/762 ,  H01L27/11573 ,  H01L21/76 ,  H01L29/06

    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices.

    Transistor layout to reduce kink effect
    69.
    发明授权
    Transistor layout to reduce kink effect 有权

    公开(公告)号：US10510855B2

    公开(公告)日：2019-12-17

    申请号：US15989606

    申请日：2018-05-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

    IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

    Abstract: The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions.

    Metal gate modulation to improve kink effect
    70.
    发明授权
    Metal gate modulation to improve kink effect 有权

    公开(公告)号：US10468410B2

    公开(公告)日：2019-11-05

    申请号：US15989648

    申请日：2018-05-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

    IPC: H01L21/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

    Abstract: In some embodiments, the present disclosure, relates to an integrated chip. The integrated chip has an isolation structure arranged within a substrate. The isolation structure has interior surfaces defining one or more divots recessed below an uppermost surface of the isolation structure and sidewalls defining an opening exposing the substrate. A source region is disposed within the opening. A drain region is also disposed within the opening and is separated from the source region by a channel region along a first direction. A gate structure extends over the channel region. The gate structure includes a first gate electrode region having a first composition of one or more materials and a second gate electrode region disposed over the one or more divots and having a second composition of one or more materials different than the first composition of one or more materials.

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