公开(公告)号：US08716755B2

公开(公告)日：2014-05-06

申请号：US13553759

申请日：2012-07-19

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.

摘要翻译： 在帽层和阻挡层之间的界面处产生压缩应变，并且在沟道层和缓冲层之间的界面处产生压缩应变，并且在阻挡层和沟道层之间的界面处产生拉伸应变。 因此，负电荷高于帽层和阻挡层之间的界面处的正电荷以及沟道层与缓冲层之间的界面，而正电荷高于阻挡层和沟道之间的界面处的负电荷 。 沟道层具有第一层，第二层和第三层的堆叠层结构。 第二层比第一层和第三层具有更高的电子亲和力。

公开(公告)号：US09123739B2

公开(公告)日：2015-09-01

申请号：US13548078

申请日：2012-07-12

申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/737 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US20130037868A1

公开(公告)日：2013-02-14

申请号：US13548078

申请日：2012-07-12

申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US06534790B2

公开(公告)日：2003-03-18

申请号：US09796803

申请日：2001-03-02

申请人： Takehiko Kato ,  Kazuki Ota ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Masaaki Kuzuhara

发明人： Takehiko Kato ,  Kazuki Ota ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Masaaki Kuzuhara

IPC分类号： H01L2915

CPC分类号： H01L29/66462 ,  H01L29/7785

摘要： The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.

摘要翻译： 本发明提供一种在半绝缘化合物半导体衬底上具有缓冲层的场效应晶体管（FET） 包括由第一导电型外延生长层（例如InGaAs）制成的沟道层的有源层; 源极/漏极，形成在形成在所述有源层上或其侧面上的第一导电型接触层上; 由第二导电型外延生长层（例如p + -GaAs）制成的栅极层; 以及形成在所述栅极层上的栅电极; 在所述第二导电型栅极层和所述沟道层之间还具有快速降低从所述栅极层扩散到所述沟道层的能带的能量的半导体层（例如InGaP）。 本发明提高了在栅极区（JFET）中具有pn结的FET的耐压特性，并且实现了JFET的稳定操作。

公开(公告)号：US5801405A

公开(公告)日：1998-09-01

申请号：US923067

申请日：1997-09-03

申请人： Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/1029 ,  H01L29/7783

摘要： An active layer of a field effect transistor disposed on an InP substrate (101) comprises at least an InAs layer (105) and two InGaAs layers (104, 106). The InGaAs layer (104) is In.sub.x Ga.sub.1-x As (wherein 0.55

摘要翻译： 设置在InP衬底（101）上的场效应晶体管的有源层至少包括InAs层（105）和两个InGaAs层（104,106）。 InGaAs层（104）是In x Ga 1-x As（其中0.55

公开(公告)号：US5608239A

公开(公告)日：1997-03-04

申请号：US357216

申请日：1994-12-13

申请人： Hironobu Miyamoto ,  Tatsuo Nakayama

发明人： Hironobu Miyamoto ,  Tatsuo Nakayama

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/7783

摘要： The present invention relates to a field effect transistor with high speed and excellent high frequency characteristics. A hetero junction field effect transistor, comprising a first semiconductor layer that contains In, a second semiconductor layer that contains In whose composition ratio is smaller than that of the first semiconductor layer, and a third semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are successively disposed in the order, and wherein the thickness of the second semiconductor layer is equal to or larger than the thickness of two monolayers thereof and less than 4 nm. A current of this field effect transistor flows in the first semiconductor layer 3 and the second semiconductor layer 4 of the transistor. When the thickness of the second semiconductor layer 4 is 4 nm or more, the ratio of electrons that exist in the first semiconductor layer 3 is 85% or less of the case that the thickness of the second semiconductor layer 4 is almost zero. Thus, when the thickness of the second semiconductor layer 4 is decreased to the thickness of two monolayers thereof, the ratio of electrons that exist in the first semiconductor layer 3 becomes nearly 100%. Consequently, the high frequency characteristics of the transistor are improved.

摘要翻译： 本发明涉及具有高速度和优异的高频特性的场效应晶体管。 一种异质结场效应晶体管，包括含有In的第一半导体层，包含其组成比小于第一半导体层的组成比的第二半导体层，以及第三半导体层，其电子亲和力小于 第一半导体层，其中第一半导体层，第二半导体层和第三半导体层依次依次布置，并且其中第二半导体层的厚度等于或大于其两个单层的厚度和更小的厚度 超过4nm。 该场效应晶体管的电流在晶体管的第一半导体层3和第二半导体层4中流动。 当第二半导体层4的厚度为4nm以上时，在第二半导体层4的厚度几乎为零的情况下，存在于第一半导体层3中的电子的比例为85％以下。 因此，当第二半导体层4的厚度减小到其两个单层的厚度时，存在于第一半导体层3中的电子的比例接近100％。 因此，提高了晶体管的高频特性。

公开(公告)号：US08618578B2

公开(公告)日：2013-12-31

申请号：US13147676

申请日：2010-02-03

申请人： Kazuki Ota ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Kazuki Ota ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/4236 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66621 ,  H01L29/7783 ,  H01L29/7787

摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0

摘要翻译： 场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112） ，其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。 所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105） 其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。 氮化物类半导体多层结构中的各层的Al组成满足0

公开(公告)号：US20110291160A1

公开(公告)日：2011-12-01

申请号：US13147676

申请日：2010-02-03

申请人： Kazuki Ota ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Kazuki Ota ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/778

CPC分类号： H01L29/4236 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66621 ,  H01L29/7783 ,  H01L29/7787

摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0

摘要翻译： 场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112） ，其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。 所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0＆lt; n 1; 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105） 其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。 氮化物系半导体多层结构中的各层的Al组成满足0

公开(公告)号：US20100155779A1

公开(公告)日：2010-06-24

申请号：US11992755

申请日：2006-09-28

申请人： Yasuhiro Murase ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Kouji Matsunaga ,  Hironobu Miyamoto

发明人： Yasuhiro Murase ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Kouji Matsunaga ,  Hironobu Miyamoto

IPC分类号： H01L29/78

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/405 ,  H01L29/66462

摘要： In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode 101 and a drain electrode 103 formed apart from each other over the Group III nitride semiconductor layer structure, and a gate electrode 102 disposed between these electrodes, are provided. Over the surface of the Group III nitride semiconductor layer structure, a SiO2 film 122 containing oxygen as a constitutive element is provided, in contact with both side faces of the gate electrode 102. Over the surface of the Group III nitride semiconductor layer structure, a SiN film 121 is provided so as to cover the region between the SiO2 film 122 and the source electrode 101, and the region between the SiO2 film 122 and the drain electrode 103. The SiN film 121 is composed of a material different from that composing the SiO2 film 122, and contains nitrogen as a constitutive element.

摘要翻译： 在场效应晶体管中，包含异质结的III族氮化物半导体层结构，在III族氮化物半导体层结构上彼此分开形成的源电极101和漏极103以及设置在这些电极之间的栅极102 ，提供。 在III族氮化物半导体层结构的表面上，提供含有氧作为构成元素的SiO 2膜122，与栅电极102的两个侧面接触。在III族氮化物半导体层结构的表面上， SiN膜121被设置为覆盖SiO 2膜122和源电极101之间的区域以及SiO 2膜122和漏电极103之间的区域。SiN膜121由与不同于构成 SiO 2膜122，并且含有氮作为构成元素。

公开(公告)号：US08930614B2

公开(公告)日：2015-01-06

申请号：US13560486

申请日：2012-07-27

申请人： Yoko Masuo ,  Yoshimasa Aoyama ,  Hironobu Miyamoto

发明人： Yoko Masuo ,  Yoshimasa Aoyama ,  Hironobu Miyamoto

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： According to one embodiment, a data storage apparatus includes a flash memory and a controller. The controller includes a compaction processor. The compaction processor performs the compaction processing on the flash memory, to dynamically set a range of compaction processing targets based on a number of available blocks and an amount of valid data in each of the blocks, and to search the range of compaction processing targets for blocks each with a relatively small amount of valid data as the target blocks for the compaction processing.

摘要翻译： 根据一个实施例，数据存储装置包括闪速存储器和控制器。 控制器包括压缩处理器。 压缩处理器对闪速存储器执行压缩处理，基于可用块的数量和每个块中的有效数据量来动态地设置压缩处理目标的范围，并且搜索压缩处理目标的范围 阻止每个具有相对少量的有效数据作为压缩处理的目标块。