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    Semiconductor device and manufacturing method of semiconductor device
    1.
    发明授权
    Semiconductor device and manufacturing method of semiconductor device 有权
    半导体器件及半导体器件的制造方法

    公开(公告)号：US09123739B2

    公开(公告)日：2015-09-01

    申请号：US13548078

    申请日：2012-07-12

    申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

    发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

    IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/737 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20

    CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

    摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

    摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

    Semiconductor device and manufacturing method of the same
    4.
    发明授权
    Semiconductor device and manufacturing method of the same 失效
    半导体器件及其制造方法相同

    公开(公告)号：US08426895B2

    公开(公告)日：2013-04-23

    申请号：US12735817

    申请日：2009-03-23

    申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    IPC分类号： H01L29/205

    CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66734

    摘要： A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2′) is formed on a substrate (1′). A p-type conductive layer (3′) is formed thereon. A second n-type conductive layer (4′) is formed thereon. On the under surface of the substrate (1′), there is a drain electrode (13′) connected to the first n-type conductive layer (2′). On the upper surface of the substrate (1′), there is a source electrode (11′) in ohmic contact with the second n-type conductive layer (4′), and a gate electrode (12′) in contact with the first n-type conductive layer (2′), p-type conductive layer (3′), the second n-type conductive layer (4′) through an insulation film (21′). The gate electrode (12′) and the source electrode (11′) are alternately arranged. The p-type conductive layer (3′) includes In.

    摘要翻译： 提供能够抑制穿通现象发生的半导体器件。 在基板（1'）上形成第一n型导电层（2'）。 在其上形成p型导电层（3'）。 在其上形成第二n型导电层（4'）。 在基板（1'）的下表面上，连接有第一n型导电层（2'）的漏电极（13'）。 在基板（1'）的上表面上存在与第二n型导电层（4'）欧姆接触的源电极（11'）和与第一n型导电层（4'）接触的栅电极（12'） n型导电层（2'），p型导电层（3'），通过绝缘膜（21'）的第二n型导电层（4'）。 栅电极（12'）和源电极（11'）交替排列。 p型导电层（3'）包括In。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08344422B2

    公开(公告)日：2013-01-01

    申请号：US12810096

    申请日：2008-12-25

    申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/778

    CPC分类号： H01L29/66462 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/7781

    摘要： A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0≦x≦1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0≦y≦1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.

    摘要翻译： 半导体器件包括在应变松弛的状态下由Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）层构成的下阻挡层12，以及由In y Ga 1-y N（0＆lt; nlE; 1）层组成的沟道层13。 y）; 1）设置在下阻挡层12上，具有小于下阻挡层12的带隙的带隙，并且表现出压缩应变。 在沟道层13上经由绝缘膜15形成栅极电极1G，在沟道层13上形成有用作欧姆电极的源电极1S和漏电极1D。绝缘膜15由多晶或非晶构成。

    SEMICONDUCTOR DEVICE, FIELD-EFFECT TRANSISTOR, AND ELECTRONIC DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE, FIELD-EFFECT TRANSISTOR, AND ELECTRONIC DEVICE 有权
    半导体器件，场效应晶体管和电子器件

    公开(公告)号：US20120228674A1

    公开(公告)日：2012-09-13

    申请号：US13497557

    申请日：2010-06-16

    申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

    摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.

    摘要翻译： 提供能够抑制穿通现象发生的半导体装置。 半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和 栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。 漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分 从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分 栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触 待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷 没有电极。

    HETEROJUNCTION FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING HETEROJUNCTION FIELD EFFECT TRANSISTOR, AND ELECTRONIC DEVICE
    7.
    发明申请
    HETEROJUNCTION FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING HETEROJUNCTION FIELD EFFECT TRANSISTOR, AND ELECTRONIC DEVICE 有权
    异相场效应晶体管，用于产生异相场效应晶体管的方法和电子器件

    公开(公告)号：US20110284865A1

    公开(公告)日：2011-11-24

    申请号：US13141449

    申请日：2009-12-25

    申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

    发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

    摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

    摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

    III-nitride semiconductor field effect transistor
    8.
    发明授权
    III-nitride semiconductor field effect transistor 有权
    III族氮化物半导体场效应晶体管

    公开(公告)号：US07985984B2

    公开(公告)日：2011-07-26

    申请号：US12528578

    申请日：2008-02-26

    申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue

    发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue

    IPC分类号： H01L29/778

    CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/7781

    摘要： Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate (101); an undercoat layer (103) of a first III-nitride semiconductor; and a carrier travel layer (104) of a second III-nitride semiconductor. The undercoat layer (103) (101) and the carrier travel layer (104) is formed on the substrate in this order. The field effect transistor includes source/drain electrodes (105, 106) in ohmic contact, and a gate electrode (107) in Schottky contact directly or via another layer on the carrier travel layer (104). The undercoat layer (103) has an average lattice constant greater than that of the carrier travel layer (104) and a band gap greater than that of the carrier travel layer (104).

    摘要翻译： 提供了能够降低接触电阻，具有小的电流崩溃的半导体器件，并且可以在高频操作时提高夹断特性。 使用纤锌矿（具有（0001）作为主面）的III型氮化物半导体的场效应晶体管包括：衬底（101）; 第一III族氮化物半导体的底涂层（103） 和第二III族氮化物半导体的载流子行进层（104）。 底涂层（103）（101）和载体移动层（104）依次形成在基板上。 场效应晶体管包括欧姆接触的源极/漏极（105,106）和直接或通过载流子行进层（104）上的另一层的肖特基接触的栅电极（107）。 底涂层（103）的平均晶格常数大于载体移动层（104）的平均晶格常数，并且带隙大于载流子行进层（104）的平均晶格常数。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07859014B2

    公开(公告)日：2010-12-28

    申请号：US11571290

    申请日：2005-06-24

    申请人： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Ando ,  Masaaki Kuzuhara ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Koji Hataya

    发明人： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Ando ,  Masaaki Kuzuhara ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Koji Hataya

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/78

    摘要： The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side. Such a recess structure is employed so as to provide the high-output semiconductor device capable of performing the high-voltage operation.

    摘要翻译： 本发明提供一种能够抑制电流塌陷以及防止电介质击穿电压和增益降低的半导体器件，从而进行高压操作并实现理想的高输出。 在基板（101）上形成有由第一GaN基半导体构成的缓冲层（102），由第二GaN基半导体构成的载流子移动层（103）和由 第三GaN基半导体。 通过消除第一绝缘膜（107）的一部分和载体供给层（104）的一部分来制造凹陷结构（108）。 接下来，沉积栅极绝缘膜（109），然后形成栅极电极（110），以填充凹部（108）并覆盖在第一绝缘膜（107）保留的区域上，使得 其漏电极侧的部分比源电极侧的部分长。 采用这样的凹部结构来提供能够执行高电压操作的高输出半导体器件。