公开(公告)号：US5892936A

公开(公告)日：1999-04-06

申请号：US879520

申请日：1997-06-20

申请人： Thang M. Tran ,  James K. Pickett ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  James K. Pickett ,  Rupaka Mahalingaiah

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3812 ,  G06F9/30101 ,  G06F9/30152 ,  G06F9/3016 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3832 ,  G06F9/3842

摘要： A superscalar microprocessor configured to speculatively generate register values associated with a particular register is provided. Multiple register values are generated in parallel, wherein each speculatively generated register value accounts for modifications of the register value by each of the instructions prior to the instruction for which the register value is generated. Instructions which are dependent upon each other for the register values thus generated may be executed concurrently. In one specific embodiment, the present microprocessor generates register values for the ESP register. The speculatively generated register value resulting from the modifications performed by the instructions decoded during a clock cycle is stored in a speculative register file along with constants used to generate the register value associated with each individual instruction. When a mispredicted branch instruction is detected, the register value generated during the decode of the mispredicted branch instruction may be adjusted using the stored constants. The adjustment performed reflects the value of the register at the execution of the mispredicted branch instruction.

摘要翻译： 提供了配置成推测性地生成与特定寄存器相关联的寄存器值的超标量微处理器。 并行产生多个寄存器值，其中每个推测产生的寄存器值在生成寄存器值的指令之前考虑每个指令对寄存器值的修改。 对于由此生成的寄存器值彼此依赖的指令可以同时执行。 在一个具体实施例中，本微处理器产生ESP寄存器的寄存器值。 由在时钟周期期间解码的指令执行的修改产生的推测产生的寄存器值与用于生成与每个单独指令相关联的寄存器值的常数一起存储在推测寄存器文件中。 当检测到错误预测的分支指令时，可以使用存储的常数来调整在误预测分支指令的解码期间生成的寄存器值。 执行的调整反映了在执行错误预测的分支指令时寄存器的值。

公开(公告)号：US5890006A

公开(公告)日：1999-03-30

申请号：US989794

申请日：1997-12-12

申请人： Thang M. Tran ,  Mauricio Calle ,  Shane Southard

发明人： Thang M. Tran ,  Mauricio Calle ,  Shane Southard

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/3842

摘要： A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the first microcode instruction of the cache line is identified during predecode and stored as a microcode pointer. When the cache line is scanned for dispatch, the microcode pointer is used to identify the first microcode instruction which is conveyed to the MROM unit. In another embodiment, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit. If the predicted first microcode instruction is not the actual first microcode instruction, then in a subsequent clock cycle, the actual microcode instruction is dispatched the MROM unit and the incorrectly predicted microcode instruction is canceled.

摘要翻译： 超标量微处理器预处理指令数据以识别指令的边界和指令的类型。 在一个实施例中，为了加快指令的分派，在预解码期间识别高速缓存行的第一微代码指令，并将其存储为微代码指针。 当缓存行被扫描以进行调度时，微代码指针用于识别被传送到MROM单元的第一微代码指令。 在另一个实施例中，预测第一扫描指令是微代码指令，并且被调度到MROM单元。 微代码扫描电路使用微代码指针和预解码数据的功能位将第一微代码指令的指令特定字节复用到MROM单元。 如果预测的第一微代码指令不是实际的第一微代码指令，则在随后的时钟周期中，实际的微代码指令被分派到MROM单元，并且错误地预测的微代码指令被取消。

公开(公告)号：US5881278A

公开(公告)日：1999-03-09

申请号：US550296

申请日：1995-10-30

申请人： Thang M. Tran ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  Rupaka Mahalingaiah

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/382 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3848

摘要： A return prediction unit is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address. These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The return prediction unit may continue to predict return addresses correctly following a mispredicted branch instruction.

摘要翻译： 提供返回预测单元，其被配置为根据包括在其中的返回堆栈存储来预测返回指令的返回地址。 返回栈存储器是被配置为存储与先前检测到的调用指令相关联的返回地址的堆栈结构。 可以在微处理器的指令处理流水线的早期为返回指令预测返回地址。 在一个实施例中，返回堆栈存储器另外存储具有每个返回地址的呼叫标签和返回标签。 呼叫标签和返回标签分别标识与返回地址相关联的呼叫和返回指令。 这些标签可以与检测到分支错误预测时传送到返回预测单元的分支标签进行比较。 可以使用比较结果来调整返回堆栈存储器相对于错误预测的内容。 返回预测单元可以继续在错误预测的分支指令之后正确地预测返回地址。

公开(公告)号：US5864707A

公开(公告)日：1999-01-26

申请号：US570242

申请日：1995-12-11

申请人： Thang M. Tran ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  Rupaka Mahalingaiah

IPC分类号： G01R31/3185 ,  G06F9/30 ,  G06F9/38 ,  G06F11/267

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3844 ,  G06F9/3848 ,  G01R31/318533 ,  G06F11/2236

摘要： A microprocessor is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The microprocessor may continue to predict return addresses correctly following a mispredicted branch instruction.

摘要翻译： 提供微处理器，其被配置为根据其中包括的返回堆栈存储来预测返回指令的返回地址。 返回栈存储器是被配置为存储与先前检测到的调用指令相关联的返回地址的堆栈结构。 可以在微处理器的指令处理流水线的早期为返回指令预测返回地址。 在一个实施例中，返回堆栈存储器另外存储具有每个返回地址的呼叫标签和返回标签。 呼叫标签和返回标签分别标识与返回地址相关联的呼叫和返回指令。这些标签可以与在检测到分支错误预测时传送到返回预测单元的分支标签进行比较。 可以使用比较结果来调整返回堆栈存储器相对于错误预测的内容。 微处理器可以在错误预测的分支指令之后继续正确地预测返回地址。

公开(公告)号：US5850532A

公开(公告)日：1998-12-15

申请号：US814628

申请日：1997-03-10

申请人： Rammohan Narayan ,  Shane A. Southard ,  Thang M. Tran

发明人： Rammohan Narayan ,  Shane A. Southard ,  Thang M. Tran

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816

摘要： An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

摘要翻译： 公开了一种用于超标量微处理器的指令扫描单元。 指令扫描单元处理与多个相邻指令字节相关联的开始，结束和功能字节信息（或预解码数据）。 开始字节信息和结束字节信息的处理是独立且并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。 另外，指示扫描单元是可扩展的。 可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。 此外，指令扫描单元与扫描并行地检测预解码数据中的错误状况以定位指令。 此外，与错误检查和扫描并行定位指令，MROM指令位于调度到MROM单元。

公开(公告)号：US5822575A

公开(公告)日：1998-10-13

申请号：US713287

申请日：1996-09-12

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3844

摘要： A prediction storage for branch predictions and information corresponding to branch instructions which are outstanding within an instruction processing pipeline of a microprocessor. A branch tag is assigned to each branch instruction and the corresponding branch prediction and prediction information is stored into the prediction storage. The branch tag is routed through the instruction processing pipeline with the branch instruction. Branch prediction information corresponding to the instruction remains within the branch prediction storage apparatus, which may be integrated into a branch predictor or coupled nearby. The branch tag may be more easily routed through the pipeline since the branch tag may include fewer bits than the corresponding branch prediction information. The branch prediction information may be updated after correct or incorrect prediction by conveying an indication of the prediction or misprediction and the branch tag of the branch instruction to the branch prediction storage apparatus.

摘要翻译： 用于分支预测的预测存储器和对应于在微处理器的指令处理流水线中突出的分支指令的信息。 分支标签被分配给每个分支指令，并且相应的分支预测和预测信息被存储到预测存储器中。 分支标签通过指令处理流水线与分支指令进行路由。 与指令相对应的分支预测信息保留在分支预测存储装置内，其可以集成到分支预测器中或耦合在附近。 分支标签可以更容易地通过流水线路由，因为分支标签可以包括比相应的分支预测信息少的比特。 可以通过将分支指令的预测或错误预测的指示和分支标签传送到分支预测存储装置，在正确或不正确的预测之后更新分支预测信息。

公开(公告)号：US5761712A

公开(公告)日：1998-06-02

申请号：US850290

申请日：1997-05-05

申请人： Thang M. Tran ,  James K. Pickett

发明人： Thang M. Tran ,  James K. Pickett

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F9/52 ,  G06F12/126 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

摘要： A data memory unit having a load/store unit and a data cache is provided which allows store instructions that are part of a load-op-store instruction to be executed with one access to a data cache. The load/store unit is configured with a load/store buffer having a checked bit and a way field for each buffer storage location. For load-op-store instructions, the checked bit associated with the store portion of the of the instruction is set when the load portion of the instruction accesses and hits the data cache. Also, the way field associated with the store portion is set to the way of the data cache in which the load portion hits. The data cache is configured with a locking mechanism for each cache line stored in the data cache. When the load portion of a load-op-store instruction is executed, the associated line is locked such that the line will remain in the data cache until a store instruction executes. In this way, the store portion of the load-op-store instruction is guaranteed to hit the data cache. The store may then store its data into the data cache without first performing a read cycle to determine if the store address hits the data cache.

摘要翻译： 提供具有加载/存储单元和数据高速缓存的数据存储单元，其允许作为加载操作存储指令的一部分的存储指令通过对数据高速缓存的一次访问来执行。 加载/存储单元配置有具有每个缓冲存储位置的检查位和方式字段的加载/存储缓冲器。 对于加载操作存储指令，当指令的加载部分访问并且命中数据高速缓冲存储器时，设置与指令的存储部分相关联的检查位。 此外，与存储部分相关联的方式字段被设置为加载部分命中的数据高速缓存的方式。 数据高速缓存配置有存储在数据高速缓存中的每个高速缓存行的锁定机制。 当执行加载操作存储指令的加载部分时，相关联的行被锁定，使得行将保留在数据高速缓存中直到存储指令执行。 以这种方式，加载操作存储指令的存储部分被保证命中数据高速缓存。 然后，存储器可以将其数据存储到数据高速缓存中，而不首先执行读取周期以确定存储地址是否触发数据高速缓存。

公开(公告)号：US09672044B2

公开(公告)日：2017-06-06

申请号：US13564490

申请日：2012-08-01

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F15/76 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： A processor may efficiently implement register renaming and checkpoint repair even in instruction set architectures with large numbers of wide (bit-width) registers by (i) renaming all destination operand register targets, (ii) implementing free list and architectural-to-physical mapping table as a combined array storage with unitary (or common) read, write and checkpoint pointer indexing and (iiii) storing checkpoints as snapshots of the mapping table, rather than of actual register contents. In this way, uniformity (and timing simplicity) of the decode pipeline may be accentuated and architectural-to-physical mappings (or allocable mappings) may be efficiently shuttled between free-list, reorder buffer and mapping table stores in correspondence with instruction dispatch and completion as well as checkpoint creation, retirement and restoration.

公开(公告)号：US09170818B2

公开(公告)日：2015-10-27

申请号：US13094110

申请日：2011-04-26

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3863

摘要： A data processing device maintains register map information that maps accesses to architectural registers, as identified by instructions being executed, to physical registers of the data processing device. In response to determining that an instruction, such as a speculatively-executing conditional branch, indicates a checkpoint, the data processing device stores the register map information for subsequent retrieval depending on the resolution of the instruction. In addition, in response to the checkpoint indication the data processing device generates new register map information such that accesses to the architectural registers are mapped to different physical registers. The data processing device maintains a list, referred to as a free register list, of physical registers available to be mapped to an architectural registers.

摘要翻译： 数据处理设备维护寄存器映射信息，其将对正在执行的指令识别的架构寄存器的访问映射到数据处理设备的物理寄存器。 响应于确定诸如推测执行条件分支的指令指示检查点，数据处理设备根据指令的分辨率存储用于后续检索的寄存器映射信息。 此外，响应于检查点指示，数据处理装置产生新的寄存器映射信息，使得对架构寄存器的访问被映射到不同的物理寄存器。 数据处理设备维护被称为自由寄存器列表的可被映射到架构寄存器的物理寄存器的列表。

公开(公告)号：US20150100965A1

公开(公告)日：2015-04-09

申请号：US14046438

申请日：2013-10-04

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F9/50

CPC分类号： G06F9/5011 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3851 ,  G06F2209/5021 ,  G06F2209/507

摘要： A method includes, in one implementation, receiving a first set of instructions of a first thread, receiving a second set of instructions of a second thread, and allocating queues to the instructions from the first and second sets. During a time when the first and second threads are simultaneously being processed, changeable number of queues to can be allocated to the first thread based on factors such as the first and/or second thread's requirements or priorities, while maintaining a minimum specified number of queues that are allocated to the first and/or second thread. When needed, one thread may be stalled so that at least the minimum number of queues remains reserved for another thread while attempting to satisfy thread-priority requests or queue-requirement requests.

摘要翻译： 一种方法包括：在一个实现中，接收第一线程的第一组指令，接收第二线程的第二组指令，以及从所述第一和第二组向所述指令分配队列。 在同时处理第一和第二线程的时间期间，可以基于诸如第一线程和/或第二线程的要求或优先级之类的因素分配给第一线程的可更改队列数，同时保持最小指定队列数 被分配给第一和/或第二线程。 当需要时，一个线程可能被停止，使得在尝试满足线程优先级请求或队列请求请求时，至少最小数量的队列保留为另一个线程。